PIC16LF876A-I Datasheet, PDF (21/234 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers

PIC16F87XA
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on: Details
POR, BOR on page:
Bank 2
100h⁽³⁾ INDF
101h TMR0
102h⁽³⁾ PCL
103h⁽³⁾ STATUS
104h⁽³⁾ FSR
105h
—
106h PORTB
107h
—
108h
—
109h
—
10Ah^(1,3) PCLATH
10Bh⁽³⁾ INTCON
10Ch EEDATA
10Dh EEADR
10Eh EEDATH
10Fh EEADRH
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 31, 150
Timer0 Module Register
xxxx xxxx 55, 150
Program Counter’s (PC) Least Significant Byte
0000 0000 30, 150
IRP
RP1
RP0
TO
PD
Z
DC
C 0001 1xxx 22, 150
Indirect Data Memory Address Pointer
xxxx xxxx 31, 150
Unimplemented
—
—
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx 45, 150
Unimplemented
—
—
Unimplemented
—
—
Unimplemented
—
—
—
—
— Write Buffer for the upper 5 bits of the Program Counter ---0 0000 30, 150
GIE
PEIE TMR0IE INTE
RBIE TMR0IF INTF
RBIF 0000 000x 24, 150
EEPROM Data Register Low Byte
xxxx xxxx 39, 151
EEPROM Address Register Low Byte
xxxx xxxx 39, 151
—
— EEPROM Data Register High Byte
--xx xxxx 39, 151
—
—
—
—⁽⁵⁾ EEPROM Address Register High Byte
---- xxxx 39, 151
Bank 3
180h⁽³⁾ INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 31, 150
181h OPTION_REG RBPU INTEDG T0CS
T0SE
PSA
PS2
PS1
PS0 1111 1111 23, 150
182h⁽³⁾ PCL
Program Counter (PC) Least Significant Byte
0000 0000 30, 150
183h⁽³⁾ STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C 0001 1xxx 22, 150
184h⁽³⁾ FSR
Indirect Data Memory Address Pointer
xxxx xxxx 31, 150
185h
—
Unimplemented
—
—
186h TRISB
PORTB Data Direction Register
1111 1111 45, 150
187h
—
Unimplemented
—
—
188h
—
Unimplemented
—
—
189h
—
18Ah^(1,3) PCLATH
18Bh⁽³⁾ INTCON
Unimplemented
—
—
GIE
PEIE
— Write Buffer for the upper 5 bits of the Program Counter
TMR0IE INTE
RBIE TMR0IF INTF
RBIF
—
—
---0 0000 30, 150
0000 000x 24, 150
18Ch EECON1
EEPGD
—
—
—
WRERR WREN
WR
RD x--- x000 34, 151
18Dh EECON2
EEPROM Control Register 2 (not a physical register)
---- ---- 39, 151
18Eh
—
Reserved; maintain clear
0000 0000 —
18Fh
—
Reserved; maintain clear
0000 0000 —
Legend:
Note 1:
2:
3:
4:
5:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter.
Bits PSPIE and PSPIF are reserved on PIC16F873A/876A devices; always maintain these bits clear.
These registers can be addressed from any bank.
PORTD, PORTE, TRISD and TRISE are not implemented on PIC16F873A/876A devices, read as ‘0’.
Bit 4 of EEADRH implemented only on the PIC16F876A/877A devices.
 2001-2013 Microchip Technology Inc.
DS39582C-page 21