PIC16LF876A-I Datasheet, PDF (193/234 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers

PIC16F87XA
FIGURE 17-17: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
RC7/RX/DT
pin
121
121
120
122
Note: Refer to Figure 17-3 for load conditions.
TABLE 17-12: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
No.
Symbol
Characteristic
Min Typ† Max Units Conditions
120 TCKH2DTV SYNC XMIT (MASTER & SLAVE)
Clock High to Data Out Valid
Standard(F)
— — 80 ns
Extended(LF) — — 100 ns
121 TCKRF
Clock Out Rise Time and Fall Time Standard(F)
— — 45 ns
(Master mode)
Extended(LF) — — 50 ns
122 TDTRF
Data Out Rise Time and Fall Time Standard(F)
— — 45 ns
Extended(LF) — — 50 ns
† Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
FIGURE 17-18: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
RC7/RX/DT
pin
125
126
Note: Refer to Figure 17-3 for load conditions.
TABLE 17-13: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Param
No.
Symbol
Characteristic
Min Typ† Max Units Conditions
125
TDTV2CKL SYNC RCV (MASTER & SLAVE)
Data Setup before CK  (DT setup time) 15
—
—
ns
126
TCKL2DTL Data Hold after CK  (DT hold time)
15
—
—
ns
† Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
 2001-2013 Microchip Technology Inc.
DS39582C-page 193