PIC16LF876A-I Datasheet, PDF (20/234 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers

PIC16F87XA
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on: Details
POR, BOR on page:
Bank 1
80h⁽³⁾ INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 31, 150
81h
82h⁽³⁾
83h⁽³⁾
84h⁽³⁾
85h
86h
87h
88h⁽⁴⁾
89h⁽⁴⁾
8Ah^(1,3)
8Bh⁽³⁾
8Ch
8Dh
OPTION_REG RBPU INTEDG T0CS
T0SE
PSA
PS2
PS1
PS0 1111 1111 23, 150
PCL
Program Counter (PC) Least Significant Byte
0000 0000 30, 150
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C 0001 1xxx 22, 150
FSR
Indirect Data Memory Address Pointer
xxxx xxxx 31, 150
TRISA
—
— PORTA Data Direction Register
--11 1111 43, 150
TRISB
PORTB Data Direction Register
1111 1111 45, 150
TRISC
PORTC Data Direction Register
1111 1111 47, 150
TRISD
PORTD Data Direction Register
1111 1111 48, 151
TRISE
IBF
OBF
IBOV PSPMODE — PORTE Data Direction bits
0000 -111 50, 151
PCLATH
—
—
— Write Buffer for the upper 5 bits of the Program Counter ---0 0000 30, 150
INTCON
PIE1
GIE
PSPIE⁽²⁾
PEIE
ADIE
TMR0IE
RCIE
INTE
TXIE
RBIE
SSPIE
TMR0IF INTF
RBIF 0000 000x 24, 150
CCP1IE TMR2IE TMR1IE 0000 0000 25, 151
PIE2
—
CMIE
—
EEIE
BCLIE
—
—
CCP2IE -0-0 0--0 27, 151
8Eh
PCON
—
—
—
—
—
—
POR
BOR ---- --qq 29, 151
8Fh
—
Unimplemented
—
—
90h
—
Unimplemented
—
—
91h
SSPCON2
GCEN ACKSTAT ACKDT ACKEN RCEN
PEN
RSEN
SEN 0000 0000 83, 151
92h
PR2
Timer2 Period Register
93h
SSPADD
Synchronous Serial Port (I²C mode) Address Register
1111 1111 62, 151
0000 0000 79, 151
94h
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF 0000 0000 79, 151
95h
—
Unimplemented
—
—
96h
—
Unimplemented
—
—
97h
—
Unimplemented
—
—
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH TRMT TX9D 0000 -010 111, 151
99h
SPBRG
Baud Rate Generator Register
0000 0000 113, 151
9Ah
—
Unimplemented
—
—
9Bh
—
Unimplemented
—
—
9Ch
CMCON
C2OUT C1OUT C2INV C1INV
CIS
CM2
CM1
CM0 0000 0111 135, 151
9Dh
CVRCON
CVREN CVROE CVRR
—
CVR3
CVR2
CVR1 CVR0 000- 0000 141, 151
9Eh
ADRESL
A/D Result Register Low Byte
xxxx xxxx 133, 151
9Fh
ADCON1
ADFM ADCS2
—
—
PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 128, 151
Legend:
Note 1:
2:
3:
4:
5:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter.
Bits PSPIE and PSPIF are reserved on PIC16F873A/876A devices; always maintain these bits clear.
These registers can be addressed from any bank.
PORTD, PORTE, TRISD and TRISE are not implemented on PIC16F873A/876A devices, read as ‘0’.
Bit 4 of EEADRH implemented only on the PIC16F876A/877A devices.
DS39582C-page 20
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