PIC16LF876A-I Datasheet, PDF (192/234 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers

PIC16F87XA
TABLE 17-11: I²C BUS DATA REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Max Units
Conditions
100 THIGH
Clock High Time
100 kHz mode
4.0
—
s
400 kHz mode
0.6
—
s
SSP Module
0.5 TCY
—
101 TLOW
Clock Low Time
100 kHz mode
4.7
—
s
400 kHz mode
1.3
—
s
SSP Module
0.5 TCY
—
102 TR
SDA and SCL Rise
Time
100 kHz mode
400 kHz mode
—
1000
20 + 0.1 CB 300
ns
ns Cb is specified to be from 10 to
400 pF
103 TF
SDA and SCL Fall
Time
100 kHz mode
400 kHz mode
—
300
20 + 0.1 CB 300
ns
ns CB is specified to be from 10 to
400 pF
90
TSU:STA Start Condition Setup 100 kHz mode
Time
400 kHz mode
4.7
—
s Only relevant for Repeated Start
0.6
—
s ^condition
91
THD:STA Start Condition Hold 100 kHz mode
Time
400 kHz mode
4.0
—
s After this period, the first clock
0.6
—
s ^{pulse is generated}
106 THD:DAT Data Input Hold Time 100 kHz mode
0
—
ns
400 kHz mode
0
0.9
s
107 TSU:DAT Data Input Setup Time 100 kHz mode
250
—
ns (Note 2)
400 kHz mode
100
—
ns
92
TSU:STO Stop Condition Setup 100 kHz mode
Time
400 kHz mode
4.7
—
s
0.6
—
s
109 TAA
Output Valid from
Clock
100 kHz mode
400 kHz mode
—
3500 ns (Note 1)
—
—
ns
110 TBUF
Bus Free Time
100 kHz mode
400 kHz mode
4.7
—
s Time the bus must be free before
1.3
—
s ^{a new transmission can start}
CB
Bus Capacitive Loading
—
400 pF
Note 1:
2:
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)
of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
A fast mode (400 kHz) I²C bus device can be used in a standard mode (100 kHz) I²C bus system, but the requirement
that, TSU:DAT  250 ns, must then be met. This will automatically be the case if the device does not stretch the LOW
period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line, TR MAX. + TSU:DAT = 1000 + 250 = 1250 ns (according to the standard mode I²C bus specification),
before the SCL line is released.
DS39582C-page 192
 2001-2013 Microchip Technology Inc.