KSZ8462HL Datasheet, PDF (62/279 Pages) Micrel Semiconductor – IEEE 1588 Precision Time Protocol-Enabled Two-Port 10/100Mb/s Ethernet Switch with 8 or 16 Bit Host Interface

Micrel, Inc.
KSZ8462HL/KSZ8462FHL
The KSZ8462 supports up to 12 timestamp input units which can input from any one of the seven GPIO pins by setting
bits[11:8] in TS[1:12]_CFG registers. The enable bits[11:0] in TS_EN register are used to enable the trigger output units.
The last timestamp input unit (unit 12) can support up to eight timestamps for multiple event detection and up to four
pulses can be detected. The rest of the units (units 1−11) have two timestamps to support single edge or pulse detection.
Pulse width can be measured by the time difference between consecutive timestamps. When an input event is detected,
one of the bits[11:0] in TS_RDY register is asserted and will generate a timestamp interrupt if the PTP_TS_IE bit is set.
The host CPU is also expected to read the timestamp status in the TS[1:12]_STATUS registers to report the number of
detected event (either rising or falling edge) counts and overflow. In single mode, it can detect up to 15 events at any
single unit. In cascade mode, it can detect up to two events at units 1−11 or up to 8 events at unit 12, and it can detect up
to 15 events for any unit as a tail unit. Pulses or edges can be detected up to 25MHz.
For more details on 1588 PTP event timestamp input control, configuration and function, please refer to the register
descriptions for locations 0x400 to 0x5FD in the register map.
IEEE 1588 PTP Event Interrupts
All IEEE 1588 PTP event trigger and timestamp interrupts are located in the PTP_TRIG_IE/PTP_TS_IE enable registers
and the PTP_TRIG_IS/PTP_TS_IS status registers. These interrupts are fully maskable via their respective enable bits
and shared with other interrupts that use the INTRN interrupt pin.
These 12 trigger output status interrupts are logical OR’ed together and connected to bit[10] in the ISR register.
These 12 trigger output enable interrupts are logical OR’ed together and connected to bit[10] in the IER register.
These 12 timestamp status interrupts are logical OR’ed together with the rest of bits in this register and the logical OR’ed
output is connected to bit [2] in the ISR register.
These 12 timestamp enable interrupts are logical OR’ed together with the rest of bits in this register and the logical OR’ed
output is connected to bit[12] in the IER register.
IEEE 1588 GPIO
The KSZ8462 supports seven GPIO pins that can be used for general I/O or can be configured to utilize the timing of the
IEEE 1588 protocol. These GPIO pins can be used for input event monitoring, outputting pulses, outputting clocks, or
outputting unique serial bit streams. The GPIO output pins can be configured to initiate their output upon the occurrence
of a specific time which is being kept by the onboard precision time clock. Likewise, the specific time of arrival of an input
event can be captured and recorded with respect to the precision time clock. Refer to the General Purpose and IEEE
1588 Input/Output (GPIO) section for details on the operation of the GPIO pins.
June 11, 2014
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Revision 1.0