KSZ8462HL Datasheet, PDF (59/279 Pages) Micrel Semiconductor – IEEE 1588 Precision Time Protocol-Enabled Two-Port 10/100Mb/s Ethernet Switch with 8 or 16 Bit Host Interface

Micrel, Inc.
KSZ8462HL/KSZ8462FHL
Updating the System time Clock
The KSZ8462 provides four mechanisms for updating the system time clock, specifically:
• Directly set the time
• Step time adjustment
• Continuous time adjustment
• Temporary time adjustment
Directly Setting or Reading the Time
Directly setting the system time clock to a value is accomplished by setting a new time in the real time clock registers
(PTP_RTC_SH/L, PTP_RTC_NSH/L and PTP_RTC_PHASE) and then setting the load PTP 1588 clock bit
(PTP_LOAD_CLK).
Directly reading the system time clock is accomplished by setting the read PTP 1588 clock bit (PTP_READ_CLK). To
avoid lower bits overflowing during reading the system time clock, a snapshot register technique is used. The value in the
system time clock will be saved into a snapshot register by setting the PTP_READ_CLK bit in PTP_CLK_CTL, and then
subsequent reads from PTP_RTC_S, PTP_RTC_NS, and PTP_RTC_PHASE will return the system time clock value. The
CPU will add the PTP_RTC_PHASE value to PTP_RTC_S and PTP_RTC_NS to get the exact real time.
Step Time Adjustment
The system time clock can be incremented in steps if desired. The nanosecond value (PTP_RTC_NSH/L) can be added
or subtracted when the PTP_STEP_ADJ_CLK bit is set. The value will be added to the system time clock if this action
occurs while the PTP_STEP_DIR bit = “1”. The value will be subtracted from the system time clock if this action occurs
while the PTP_STEP_DIR bit = “0”. The PTP_STEP_ADJ_CLK bit is self−clearing.
Continuous Time Adjustment
The system can be set up to perform continuous time adjustment to the 1588 PTP clock. This is the mode that is
anticipated to be used the most. This mode is overseen by the local processor and provides a method of periodically
adjusting the count of the PTP clock to match the time of the master clock as best as possible. The rate registers
(PTP_SNS_RATE_H and PTP_SNS_RATE_L) (0x610 – 0x613) are used to provide a value by which the Sub
nanosecond portion of the clock is adjusted on a periodic basis. While continuous adjustment mode
(PTP_CONTINU_ADJ_CLK = “1”) is selected, every 40ns the sub-nanosecond value of the clock will be adjusted in either
a positive or negative direction as determined by the PTP_RATE_DIR bit. The value will be positively adjusted if
PTP_RATE_DIR = “0” or negatively adjusted if PTP_RATE_DIR = “1”. The rate adjustment allows for correction with
resolution of 2^−32ns for every 40ns reference clock cycle, and it will be added to or subtracted from the system time clock
on every reference clock cycle right after the write to PTP_SNC_RATE_L is done. To stop the continuous time
adjustment, one can either set the PTP_CONTINU_ADJ_CLK = “0” or the PTP_SNS_RATE_H/L value to zero.
Temporary Time Adjustment
This mode allows for the continuous time adjustment to take place over a specified period of time only. The period of time
is specified in the PTP_ADJ_DURA_H/L registers. This mode is enabled by setting the PTP_TEMP_ADJ_CLK bit to one.
Once the duration is reached, the increment or decrement will cease. When the temporary time adjustment is done, the
internal duration counter register (PTP_ADJ_DURA_H/L) will stay at zero, which will disable the time adjustment. The
local processor needs to set the PTP_TEMP_ADJ_CLK to one again to start another temporary time adjustment with the
reloaded value into the internal rate and duration registers. The PTP_ADJ_DURA_L register needs to be programmed
before PTP_ADJ_DURA_H register. The PTP_ADJ_DURA_L, PTP_ADJ_DURA_H and PTP_SNS_RATE_L registers
need to be programmed before the PTP_SNS_RATE_H register. The temporary time adjustment will start after the
PTP_TEMP_ADJ_CLK bit is set to one. This bit is self-cleared when the adjustment is completed. Software can read this
bit to check whether the adjustment is still in progress.
June 11, 2014
59
Revision 1.0