KSZ8462HL Datasheet, PDF (31/279 Pages) Micrel Semiconductor – IEEE 1588 Precision Time Protocol-Enabled Two-Port 10/100Mb/s Ethernet Switch with 8 or 16 Bit Host Interface

Micrel, Inc.
KSZ8462HL/KSZ8462FHL
Physical (PHY) Block
100BASE−TX Transmit
The 100BASE−TX transmit function performs parallel−to−serial conversion, 4B/5B coding, scrambling, NRZ−to−NRZI
conversion, and MLT3 encoding and transmission.
The circuitry starts with a parallel−to−serial conversion, which converts the MII data from the MAC into a 125MHz serial bit
stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized data is
further converted from NRZ−to−NRZI format, and then transmitted in MLT3 current output. An external 6.49KΩ (1%)
resistor for the 1:1 transformer ratio sets the output current.
The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP−PMD standard regarding amplitude
balance, overshoot, and timing jitter. The wave−shaped 10BASE−T output driver is also incorporated into the
100BASE−TX driver.
100BASE−TX Receive
The 100BASE−TX receiver function performs adaptive equalization, DC restoration, MLT3−to−NRZI conversion, data and
clock recovery, NRZI−to−NRZ conversion, de−scrambling, 4B/5B decoding, and serial−to−parallel conversion.
The receiving side starts with the equalization filter to compensate for inter−symbol interference (ISI) over the twisted pair
cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer has to adjust its
characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on
comparisons of incoming signal strength against some known cable characteristics, and then tunes itself for optimization.
This is an ongoing process and self−adjusts against environmental changes such as temperature variations.
Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is used to
compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion circuit
converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used
to convert the NRZI signal into the NRZ format. This signal is sent through the de−scrambler followed by the 4B/5B
decoder. Finally, the NRZ serial data is converted to an MII format and provided as the input data to the MAC.
Scrambler/De−Scrambler (100BASE−TX Only)
The purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic interference (EMI)
and baseline wander.
Transmitted data is scrambled through the use of an 11−bit wide linear feedback shift register (LFSR). After the scrambler
generates a 2047−bit non−repetitive sequence, the receiver de−scrambles the incoming data stream using the same
sequence as at the transmitter.
PLL Clock Synthesizer (Recovery)
The internal PLL clock synthesizer generates 125MHz, 62.5MHz and 31.25MHz clocks for the KSZ8462 system timing.
These internal clocks are generated from an external 25MHz crystal or oscillator. Refer to the Device Clocks section for
more detailed information.
100BASE−FX Operation
Fiber Mode is available only on the KSZ8462FHL device.
100BASE−FX operation is similar to 100BASE−TX operation except that the scrambler/de−scrambler and MLT3
encoder/decoder are bypassed on transmission and reception. In this fiber mode, the auto−negotiation feature is
bypassed and auto MDI/MDIX is disabled since there is no standard that supports fiber auto−negotiation and auto
MDI/MDIX mode. The fiber port must be forced to either full−duplex or half−duplex mode.
All KSZ8462 devices are in copper mode (10BASE-T / 100BASE-TX) when reset or powered on. Fiber mode is enabled
by clearing bits[7:6] in the CFGR register (0x0D8-0x0D9). Each port is individually configurable. Bit [13] in the
DSP_CNTRL_6 register (0x734-0x735) should also be cleared if either (or both) ports are set to fiber mode.
June 11, 2014
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Revision 1.0