KSZ8462HL Datasheet, PDF (199/279 Pages) Micrel Semiconductor – IEEE 1588 Precision Time Protocol-Enabled Two-Port 10/100Mb/s Ethernet Switch with 8 or 16 Bit Host Interface

Micrel, Inc.
KSZ8462HL/KSZ8462FHL
EEPROM Control Register (0x122 – 0x123): EEPCR
To support an external EEPROM, the PME/EEPROM pin should be pulled−up to high; otherwise, it should be
pulled−down to low. If an external EEPROM is not used, the software should program the host MAC address. If an
EEPROM is used in the design, the chip host MAC address can be loaded from the EEPROM immediately after reset.
The KSZ8462 allows the software to access (read or write) the EEPROM directly; that is, the EEPROM access timing can
be fully controlled by the software if the EEPROM software access bit is set.
Bit
15−6
5
4
3
2
1
0
Default Value
−
0
0
−
0
0
0
R/W Description
RO Reserved
EESRWA EEPROM Software Read or Write Access
WO 0 = S/W read enable to access EEPROM when software access enabled (bit[4] = “1”)
1 = S/W write enable to access EEPROM when software access enabled (bit[4] = “1”)
EESA EEPROM Software Access
RW 1 = Enable software to access EEPROM through bits[3:0].
0 = Disable software to access EEPROM.
EESB EEPROM Status Bit
RO
Data Receive from EEPROM. This bit directly reads the EEDIO pin.
EECB_EEPROM_WR_DATA
RW
Write Data to EEPROM. This bit directly controls the device’s EEDIO pin.
EECB_EEPROM_Clock
RW
Serial EEPROM Clock. This bit directly controls the device’s EESK pin.
EECB_EEPROM_CS
RW
Chip Select for the EEPROM. This bit directly controls the device’s EECS pin.
Memory BIST Info Register (0x124 – 0x125): MBIR
This register indicates the built−in self-test results for both TX and RX memories after power−up/reset. The device should
be reset after the BIST procedure to ensure proper subsequent operation.
Bit
15
14−13
12
11
10−8
7−5
Default Value
0
00
−
−
−
−
R/W Description
Memory BIST Done
RO 0 = BIST In progress
1 = BIST Done
RO Reserved
TXMBF TX Memory BIST Completed
RO _{0 = TX Memory built-in self-test has not completed.}
1 = TX Memory built-in self-test has completed.
TXMBFA TX Memory BIST Failed
RO _{0 = TX Memory built-in self-test has completed without failure.}
1 = TX Memory built-in self-test has completed with failure.
TXMBFC TX Memory BIST Fail Count
RO 0 = TX Memory built-in self test completed with no count failure.
1 = TX Memory built-in self test encountered a failed count condition.
RO Reserved
June 11, 2014
199
Revision 1.0