KSZ8462HL Datasheet, PDF (220/279 Pages) Micrel Semiconductor – IEEE 1588 Precision Time Protocol-Enabled Two-Port 10/100Mb/s Ethernet Switch with 8 or 16 Bit Host Interface

Micrel, Inc.
KSZ8462HL/KSZ8462FHL
Internal I/O Register Space Mapping for the Queue Management Unit (QMU)
(0x19C – 0x1B9)
RX Frame Count and Threshold Register (0x19C – 0x19D): RXFCTR
This register is used to program the received frame count threshold.
Bit
15−8
7−0
Default Value
0x00
0x00
R/W Description
RW Reserved
RXFCT Receive Frame Count Threshold
This register is used to program the received frame count threshold value.
RW When bit [5] set to “1” in the RXQCR register, the device will set interrupt bit [13] in the ISR when
the number of received frames in RXQ buffer exceeds the threshold set in this register. The
count has to be at least equal to or greater than “1” to enable correct functioning of the hardware.
A write of “1” to this register while the receive is enabled will result in erratic hardware operation.
TX Next Total Frames Size Register (0x19E – 0x19F): TXNTFSR
This register is used by the Host CPU to program the total amount of TXQ buffer space requested for the next transmit.
Bit
15−0
Default Value
0x0000
R/W Description
TXNTFSR TX Next TXQ Buffer Frame Space Required
The Host CPU programs the contents of this register to indicate the total amount of TXQ buffer
space which is required for the next “one-frame” transmission. It contains the frame size in
RW double−word count (multiples of four bytes).
When bit [1] (TXQ memory available monitor) is set to “1” in the TXQCR register, the device will
generate interrupt (bit [6] in the ISR register) to the CPU when TXQ memory is available based
upon the total amount of TXQ space requested by the CPU in this register.
MAC Address Hash Table Register 0 (0x1A0 – 0x1A1): MAHTR0
The 64−bit MAC address table is used for group address filtering and it is enabled by selecting item 5 “Hash perfect”
mode in Table 2. This value is defined as the six most significant bits from CRC circuit calculation result that is based on
48−bit of DA input. The two most significant bits select one of the four registers to be used, while the others determine
which bit within the register.
Multicast Table Register 0
Bit Default Value
R/W
15−0
0x0000
RW
Description
HT0 Hash Table 0
When the appropriate bit is set, if the packet received with DA matches the CRC, the
hashing function is received without being filtered.
When the appropriate bit is cleared, the packet will be dropped.
Note: When ”Receive All” (RXCR1, bit[4]) and the “Receive Multicast Addr. Filtering with the
MAC Address” (RXCR1, bit[8]) bit is set, all multicast addresses are received regardless of
the multicast table value.
June 11, 2014
220
Revision 1.0