MAX1126 Datasheet, PDF(6/25 Page) Maxim Integrated Products – Quad, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs

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MAX1126 Datasheet, PDF (6/25 Pages) Maxim Integrated Products – Quad, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs

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Quad, 12-Bit, 40Msps, 1.8V ADC with

Serial LVDS Outputs

ELECTRICAL CHARACTERISTICS (continued)

(AVDD = 1.8V, OVDD = 1.8V, CVDD = 1.8V, GND = 0, external VREFIO = 1.24V, INTREF = AVDD, CREFIO to GND = 0.1ÂµF,

fCLK = 40MHz (50% duty cycle), DT = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25Â°C.) (Note 1)

PARAMETER

SYMBOL

CHANNEL-TO-CHANNEL MATCHING

Crosstalk

Gain Matching

Phase Matching

CONDITIONS

(Note 2)

fIN = 19.3MHz (Note 2)

fIN = 19.3.MHz (Note 2)

MIN TYP MAX UNITS

-90

Â±0.1

Â±1

Degrees

Note 1: Specifications at TA â¥ +25Â°C are guaranteed by production testing. Specifications at TA < +25Â°C are guaranteed by design

and characterization and not subject to production testing.

Note 2: See definition in the Parameter Definitions section.

Note 3: The MAX1126 internally sets the common-mode voltage to 0.6V (typ) (see Figure 1). The common-mode voltage can be

overdriven to between 0.55V and 0.85V.

Note 4: Limited by MAX1127EVKIT input circuitry.

Note 5: Connect INTREF to GND directly to enable internal reference mode. Connect INTREF to AVDD directly to disable the internal

bandgap reference and enable external reference mode.

Note 6: Data valid to CLKOUT rise/fall timing is measured from 50% of data output level to 50% of clock output level.

Note 7: Guaranteed by design and characterization. Not subject to production testing.

Note 8: Sample CLK Rise to FRAME RISE timing is measured from 50% of sample clock input level to 50% of FRAME output level.

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