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MAX1126 Datasheet, PDF (3/25 Pages) Maxim Integrated Products – Quad, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs
Quad, 12-Bit, 40Msps, 1.8V ADC with
Serial LVDS Outputs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = 1.8V, OVDD = 1.8V, CVDD = 1.8V, GND = 0, external VREFIO = 1.24V, INTREF = AVDD, CREFIO to GND = 0.1µF,
fCLK = 40MHz (50% duty cycle), DT = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
Spurious-Free Dynamic Range
(Note 2)
Total Harmonic Distortion (Note 2)
Intermodulation Distortion
Third-Order Intermodulation
Aperture Jitter
Aperture Delay
Small-Signal Bandwidth
Full-Power Bandwidth
Output Noise
SYMBOL
SFDR
THD
IMD
IM3
tAJ
tAD
SSBW
LSBW
CONDITIONS
fIN = 5.3MHz at -0.5dBFS
fIN = 19.3MHz at -0.5dBFS, TA ≥ +25°C
fIN = 5.3MHz at -0.5dBFS
fIN = 19.3MHz at -0.5dBFS, TA ≥ +25°C
f1 = 12.40125MHz at -6.5dBFS,
f2 = 13.60125MHz at -6.5dBFS (Note 2)
f1 = 12.40125MHz at -6.5dBFS,
f2 = 13.60125MHz at -6.5dBFS (Note 2)
(Note 2)
(Note 2)
Input at -20dBFS (Notes 2 and 4)
Input at -0.5dBFS (Notes 2 and 4)
IN_P = IN_N
Overdrive Recovery Time
tOR
RS = 25Ω, CS = 50pF
INTERNAL REFERENCE (INTREF = GND, bypass REFIO to GND with 0.1µF)
INTREF Internal Reference Mode
Enable Voltage
(Note 5)
INTREF Low-Leakage Current
REFIO Output Voltage
VREFIO
Reference Temperature
Coefficient
TCREFIO
EXTERNAL REFERENCE (INTREF = AVDD)
INTREF External Reference Mode
Enable Voltage
(Note 5)
INTREF High-Leakage Current
REFIO Input Voltage Range
REFIO Input Current
CLOCK INPUT (CLK)
IREFIO
Input High Voltage
VCLKH
Input Low Voltage
Clock Duty Cycle
Clock Duty-Cycle Tolerance
VCLKL
MIN TYP MAX UNITS
93.7
dBc
77.3
89
-91.5
dBc
-88.7 -76.3
87.0
dBc
89.3
<0.4
1
100
100
0.35
1
dBc
psRMS
ns
MHz
MHz
LSBRMS
Clock
cycles
0.1
V
200
µA
1.18 1.24 1.30
V
100
ppm/°C
AVDD -
0.1V
V
200
µA
1.24
V
<1
µA
0.8 x
V
CVDD
0.2 x
V
CVDD
50
%
±30
%
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