MAX1126 Datasheet, PDF (19/25 Pages) Maxim Integrated Products – Quad, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs

Quad, 12-Bit, 40Msps, 1.8V ADC with
Serial LVDS Outputs
N
(V_{IN_P} -
V_{IN_N})
N+1
t_SAMPLE
CLK
N+2
N+3
N+5
N+4
6.5 CLOCK-CYCLE DATA LATENCY
N+6
N+9
N+8
N+7
(V_FRAMEP -
V_FRAMEN)*
(V_CLKOUTP -
V_CLKOUTN)
(V_{OUT_P} -
V_{OUT_N})
OUTPUT
DATA FOR
SAMPLE
N-6
*DUTY CYCLE VARIES DEPENDING ON INPUT CLOCK FREQUENCY.
Figure 3. Global Timing Diagram
OUTPUT
DATA FOR
SAMPLE N
N
(V_{IN_P} - V_{IN_N})
N+2
N+1
t_SAMPLE
t_SF
CLK
(V_FRAMEP -
V_FRAMEN)
(V_CLKOUTP -
V_CLKOUTN)
(V_{OUT_P} -
V_{OUT_N})
t_CF
D5_N-7 D6_N-7 D7_N-7 D8_N-7 D9_N-7 D10_N-7 D11_N-7 D0_N-6 D1_N-6 D2_N-6 D3_N-6 D4_N-6 D5_N-6 D6_N-6 D7_N-6 D8_N-6 D9_N-6 D10_N-6 D11_N-6 D0_N-5 D1_N-5 D2_N-5 D3_N-5 D4_N-5 D5_N-5 D6_N-5
*DUTY CYCLE DEPENDS ON INPUT CLOCK FREQUENCY.
Figure 4. Detailed Two-Conversion Timing Diagram
System Timing Requirements
Figure 3 shows the relationship between the analog
inputs, input clock, frame alignment output, serial clock
output, and serial data output. The differential analog
input (IN_P and IN_N) is sampled on the rising edge of
the CLK signal and the resulting data appears at the
digital outputs 6.5 clock cycles later. Figure 4 provides
a detailed, two-conversion timing diagram of the rela-
tionship between the inputs and the outputs.
Clock Output (CLKOUTP, CLKOUTN)
The MAX1126 provides a differential clock output that
consists of CLKOUTP and CLKOUTN. As shown in
Figure 4, the serial output data is clocked out of the
MAX1126 on both edges of the clock output. The fre-
quency of the output clock is 6 times the frequency
of CLK.
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