MAX1126 Datasheet, PDF (24/25 Pages) Maxim Integrated Products – Quad, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs

Quad, 12-Bit, 40Msps, 1.8V ADC with
Serial LVDS Outputs
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next-largest spurious
component, excluding DC offset. SFDR is specified in
decibels relative to the carrier (dBc).
Intermodulation Distortion (IMD)
IMD is the total power of the IM2 to IM5 intermodulation
products to the Nyquist frequency relative to the total
input power of the two input tones, f1 and f2. The indi-
vidual input tone levels are at -6.5dBFS. The intermodu-
lation products are as follows:
• 2nd-order intermodulation products (IM2): f1 + f2,
f2 - f1
• 3rd-order intermodulation products (IM3): 2 x f1 - f2,
2 x f2 - f1, 2 x f1 + f2, 2 x f2 + f1
• 4th-order intermodulation products (IM4): 3 x f1 - f2,
3 x f2 - f1, 3 x f1 + f2, 3 x f2 + f1
• 5th-order intermodulation products (IM5): 3 x f1 - 2 x
f2, 3 x f2 - 2 x f1, 3 x f1 + 2 x f2, 3 x f2 + 2 x f1
Third-Order Intermodulation (IM3)
IM3 is the total power of the 3rd-order intermodulation
product to the Nyquist frequency relative to the total
input power of the two input tones f1 and f2. The indi-
vidual input tone levels are at -6.5dBFS. The 3rd-order
intermodulation products are 2 x f1 - f2, 2 x f2 - f1, 2 x
f1 + f2, 2 x f2 + f1.
Small-Signal Bandwidth
A small -20dBFS analog input signal is applied to an
ADC so the signal’s slew rate does not limit the ADC’s
performance. The input frequency is then swept up to
the point where the amplitude of the digitized conver-
sion result has decreased by -3dB.
Full-Power Bandwidth
A large -0.5dBFS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by -3dB. This point is defined as full-
power input bandwidth frequency.
Gain Matching
Gain matching is a figure of merit that indicates how
well the gain of all four ADC channels is matched to
each other. For the MAX1126, gain matching is mea-
sured by applying the same 19.3MHz, -0.5dBFS analog
signal to all analog input channels. These analog inputs
are sampled at 40MHz and the maximum deviation in
amplitude is reported in dB as gain matching in the
Electrical Characteristics table.
Phase Matching
Phase matching is a figure of merit that indicates how
well the phase of all four ADC channels is matched to
each other. For the MAX1126, phase matching is mea-
sured by applying the same 19.3MHz, -0.5dBFS analog
signal to all analog input channels. These analog inputs
are sampled at 40MHz and the maximum deviation in
phase is reported in degrees as phase matching in the
Electrical Characteristics table.
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