MAX1126 Datasheet, PDF (5/25 Pages) Maxim Integrated Products – Quad, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs

Quad, 12-Bit, 40Msps, 1.8V ADC with
Serial LVDS Outputs
ELECTRICAL CHARACTERISTICS (continued)
(AV_DD = 1.8V, OV_DD = 1.8V, CV_DD = 1.8V, GND = 0, external V_REFIO = 1.24V, INTREF = AV_DD, C_REFIO to GND = 0.1µF,
f_CLK = 40MHz (50% duty cycle), DT = 0, T_A = T_MIN to T_MAX, unless otherwise noted. Typical values are at T_A = +25°C.) (Note 1)
PARAMETER
AV_DD Supply Current
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
PDALL = 0, all channels
active
246
285
f_IN =
PDALL = 0, all channels
active, DT = 1
246
mA
I_AVDD 19.3MHz at PDALL = 0, 1 channel active
76
-0.5dBFS
PDALL = 0, PD[3:0] = 1111
20
PDALL = 1, global power
down, PD[3:0] =1111, no
clock input
438
µA
OV_DD Supply Current
I_OVDD
f_IN =
19.3MHz at
-0.5dBFS
PDALL = 0, all channels
active
PDALL = 0, all channels
active, DT = 1
PDALL = 0, 1 channel active
PDALL = 0, PD[3:0] = 1111
PDALL = 1, global power-
down, PD[3:0] =1111, no
clock input
51
57
63
mA
35
30
375
µA
CV_DD Supply Current
I_CVDD
Power Dissipation
P_DISS
TIMING CHARACTERISTICS (Note 6)
Data Valid to CLKOUT Rise/Fall
t_OD
CV_DD is used only to bias ESD-protection
diodes on CLK input, Figure 2
f_IN = 19.3MHz at -0.5dBFS
f_CLK = 40MHz, Figure 5 (Notes 6 and 7)
0
mA
535
616
mW
(t_SAMPLE /
24)
- 0.15
t_SAMPLE /
24
(t_SAMPLE /
24)
+ 0.15
ns
CLKOUT Output Width High
CLKOUT Output Width Low
FRAME Rise to CLKOUT Rise
t_CH
Figure 5
t_CL
Figure 5
t_CF
Figure 4 (Note 7)
t_SAMPLE /
ns
12
t_SAMPLE /
ns
12
(t_SAMPLE /
24)
- 0.15
t_SAMPLE /
24
( t_SAMPLE /
24)
+ 0.15
ns
Sample CLK Rise to Frame Rise
t_SF
Figure 4 (Notes 7 and 8)
(t_SAMPLE/ (t_SAMPLE/ (t_SAMPLE/
2)
2)
2)
ns
+0.9 +1.3 +1.7
_______________________________________________________________________________________ 5