MAX1126 Datasheet, PDF (20/25 Pages) Maxim Integrated Products – Quad, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs

Quad, 12-Bit, 40Msps, 1.8V ADC with
Serial LVDS Outputs
Frame Alignment Output (FRAMEP, FRAMEN)
The MAX1126 provides a differential frame alignment
signal that consists of FRAMEP and FRAMEN. As
shown in Figure 4, the rising edge of the frame align-
ment signal corresponds to the first bit (D0) of the
12-bit serial data stream. The frequency of the frame
alignment signal is identical to the frequency of the
sample clock.
Serial Output Data (OUT_P, OUT_N)
The MAX1126 provides its conversion results through
individual differential outputs consisting of OUT_P and
OUT_N. The results are valid 6.5 input clock cycles
after the sample is taken. As shown in Figure 3, the out-
put data is clocked out on both edges of the output
clock, LSB (D0) first. Figure 5 provides the detailed ser-
ial output timing diagram.
Output Data Format (T/B), Transfer Functions
The MAX1126 output data format is either offset binary
or two’s complement, depending on the logic input T/B.
With T/B low, the output data format is two’s comple-
ment. With T/B high, the output data format is offset
binary. The following equations, Table 2, Figure 6, and
Figure 7 define the relationship between the digital
output and the analog input. For two’s complement
(T/B = 0):
V_{IN_P}
−
V_{IN_N}
=
FSR
×
2
×
CODE₁₀
4096
and for offset binary (T/B = 1):
t_CH
t_CL
(V_CLKOUTP -
V_CLKOUTN)
t_OD
t_OD
(V_{OUT_P} -
V_{OUT_N})
D0
D1
D2
D3
Figure 5. Serialized Output Detailed Timing Diagram
V_IN
_P
−
V_{IN_N}
=
FSR
×
2
×
CODE₁₀ −
4096
2048
where CODE₁₀ is the decimal equivalent of the digital
output code as shown in Table 2. FSR is the full-scale
range as shown in Figures 6 and 7.
Keep the capacitive load on the MAX1126 digital out-
puts as low as possible.
LVDS and SLVS Signals (SLVS/LVDS)
Drive SLVS/LVDS low for LVDS or drive SLVS/LVDS
high for scalable low-voltage signaling (SLVS) levels at
the MAX1126 outputs (OUT_P, OUT_N, CLKOUTP,
CLKOUTN, FRAMEP, and FRAMEN). See the Electrical
Characteristics table for LVDS and SLVS output voltage
levels.
LVDS Test Pattern (LVDSTEST)
Drive LVDSTEST high to enable the output test pattern
on all LVDS or SLVS output channels. The output test
pattern is 0000 1011 1101 MSB→LSB. As with the ana-
log conversion results, the test pattern data is output
Table 2. Output Code Table (V_REFIO = 1.24V)
TWO’S COMPLEMENT DIGITAL OUTPUT CODE
(T/B = 0)
OFFSET BINARY DIGITAL OUTPUT CODE
(T/B = 1)
BINARY
D11 D0
HEXADECIMAL
EQUIVALENT
OF
D11 D0
DECIMAL
EQUIVALENT
OF
D11 D0
BINARY
D11 D0
HEXADECIMAL
EQUIVALENT
OF
D11 D0
DECIMAL
EQUIVALENT
OF
D11 D0
0111 1111 1111
0111 1111 1110
0x7FF
0x7FE
+2047
+2046
1111 1111 1111
1111 1111 1110
0xFFF
0xFFE
+4095
+4094
V_{IN_P} - V_{IN_P} (mV)
(V_REFIO = 1.24V)
+699.66
+699.32
0000 0000 0001
0000 0000 0000
1111 1111 1111
0x001
0x000
0xFFF
+1
1000 0000 0001
0x801
0
1000 0000 0000
0x800
-1
0111 1111 1111
0x7FF
+2049
+2048
+2047
+0.34
0
-0.34
1000 0000 0001
0X801
-2047
0000 0000 0001
0x001
+1
1000 0000 0000
0x800
-2048
0000 0000 0000
0x000
0
20 ______________________________________________________________________________________
-699.66
-700.00