MAX1126 Datasheet, PDF (17/25 Pages) Maxim Integrated Products – Quad, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs

Quad, 12-Bit, 40Msps, 1.8V ADC with
Serial LVDS Outputs
Detailed Description
The MAX1126 ADC features fully differential inputs, a
pipelined architecture, and digital error correction for
high-speed signal conversion. The ADC pipeline archi-
tecture moves the samples taken at the inputs through
the pipeline stages every half clock cycle. The convert-
ed digital results are serialized and sent through the
LVDS/SLVS output drivers. The total latency from input
to output is 6.5 input clock cycles.
The MAX1126 offers four separate fully differential
channels with synchronized inputs and outputs.
Configure the outputs for binary or two’s complement
with the T/B digital input. Power-down each channel
individually or globally to minimize power consumption.
Input Circuit
Figure 1 displays a simplified functional diagram of the
input T/H circuits. In track mode, switches S1, S2a, S2b,
S4a, S4b, S5a, and S5b are closed. The fully differential
circuits sample the input signals onto the two capacitors
(C2a and C2b) through switches S4a and S4b. S2a and
S2b set the common mode for the operational transcon-
ductance amplifier (OTA), and open simultaneously with
S1, sampling the input waveform. Switches S4a, S4b,
S5a, and S5b are then opened before switches S3a and
S3b connect capacitors C1a and C1b to the output of
the amplifier and switch S4c is closed. The resulting dif-
ferential voltages are held on capacitors C2a and C2b.
The amplifiers charge capacitors C1a and C1b to the
same values originally held on C2a and C2b. These
values are then presented to the first-stage quantizers
and isolate the pipelines from the fast-changing inputs.
Analog inputs IN_P to IN_N are driven differentially. For
differential inputs, balance the input impedance of IN_P
and IN_N for optimum performance.
The MAX1126 analog inputs are self-biased at a com-
mon-mode voltage of 0.6V (typ) and allow a differential
input voltage swing of 1.4V_P-P. The common-mode volt-
age can be overdriven to between 0.55V and 0.85V.
Drive the analog inputs of the MAX1126 in AC-coupled
configuration to achieve best dynamic performance.
See the Using Transformer Coupling section for a
detailed discussion of this configuration.
INTERNAL
COMMON-MODE
BIAS*
INTERNAL
BIAS*
AV_DD
S2a
MAX1126
S4a
C2a
IN_P
S4c
S1
IN_N
S4b
C2b
GND
INTERNAL
COMMON-MODE
BIAS*
*NOT EXTERNALLY ACCESSIBLE
Figure 1. Internal Input Circuitry
S2b
INTERNAL
BIAS*
SWITCHES SHOWN IN TRACK MODE
INTERNALLY
GENERATED
COMMON-MODE
LEVEL*
S5a
C1a
S3a
OUT
OTA
OUT
C1b
S3b
S5b
INTERNALLY
GENERATED
COMMON-MODE
LEVEL*
______________________________________________________________________________________ 17