MAX1126 Datasheet, PDF (18/25 Pages) Maxim Integrated Products – Quad, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs

Quad, 12-Bit, 40Msps, 1.8V ADC with
Serial LVDS Outputs
Reference Configurations
(REFIO and INTREF)
The MAX1126 provides an internal 1.24V bandgap ref-
erence or can be driven with an external reference volt-
age. The MAX1126 full-scale analog differential input
range is ±FSR. Full-scale range (FSR) is given by the
following equation:
FSR = 700mV x ^VREFIO
1.24 V
where V_REFIO is the voltage at REFIO, generated inter-
nally or externally. For a V_REFIO = 1.24V, the full-scale
input range is ±700mV (1.4V_P-P).
Internal Reference Mode
Connect INTREF to GND to use the internal bandgap
reference directly. The internal bandgap reference gen-
erates REFIO to be 1.24V with a 100ppm/°C tempera-
ture coefficient in internal reference mode. Connect an
external ≥0.1µF bypass capacitor from REFIO to GND
for stability. REFIO sources up to 200µA and sinks up
to 200µA for external circuits, and REFIO has a load
regulation of 83mV/mA. The global power-down input
(PDALL) enables and disables the reference circuit.
REFIO has >1MΩ resistance to GND when the
MAX1126 is in power-down mode. The internal refer-
ence circuit requires 132µs to power-up and settle
when power is applied to the MAX1126 or when PDALL
transitions from high to low.
External Reference Mode
The external reference mode allows for more control
over the MAX1126 reference voltage and allows multi-
ple converters to use a common reference. Connect
INTREF to AV_DD to disable the internal reference and
enter external reference mode. Apply a stable 1.24V
source at REFIO. Bypass REFIO to GND with a 0.1µF
capacitor. The REFIO input impedance is >1MΩ.
Clock Input (CLK)
The MAX1126 accepts a CMOS-compatible clock sig-
nal with a wide 20% to 80% input-clock duty cycle.
Drive CLK with an external single-ended clock signal.
Figure 2 shows the simplified clock input diagram.
Low clock jitter is required for the specified SNR perfor-
mance of the MAX1126. Analog input sampling occurs
on the rising edge of CLK, requiring this edge to pro-
vide the lowest possible jitter. Jitter limits the maximum
SNR performance of any ADC according to the follow-
ing relationship:
SNR
= 20 × log
⎛
⎝⎜
2×
π
1
× f_IN
×
t_J
⎞
⎠⎟
where f_IN represents the analog input frequency and t_J
is the total system clock jitter. Clock jitter is especially
critical for undersampling applications. For example,
assuming that clock jitter is the only noise source, to
obtain the specified 69.2dB of SNR with an input fre-
quency of 19.3MHz, the system must have less than
2.8ps_RMS of clock jitter. In actuality, there are other
noise sources, such as thermal noise and quantization
noise, that contribute to the system noise requiring the
clock jitter to be less than 1.1ps_RMS to obtain the speci-
fied 69.2dB of SNR at 19.3MHz.
PLL Inputs (PLLO–PLL3)
The MAX1126 features a PLL that generates an output
clock signal with 6 times the frequency of the input
clock. The output clock signal is used to clock data out
of the MAX1126 (see the System Timing Requirements
section). Set the PLL2 and PLL3 bits according to the
input clock range provided in Table 1. PLL0 and PLL1
are reserved for factory testing and must always be
connected to GND.
AV_DD
MAX1126
CV_DD
CLK
DUTY-CYCLE
EQUALIZER
GND
Figure 2. Clock Input Circuitry
Table 1. PLL2 and PLL3 Configuration
PLL2
0
0
1
1
PLL3
0
1
0
1
CLOCK INPUT RANGE
(MHz)
MIN
MAX
NOT USED
32.500
24.375
16.000
40.000
32.500
24.375
*PLL0 and PLL11 are reserved for factory testing and must
always be connected to GND.
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