MAX1126 Datasheet, PDF (16/25 Pages) Maxim Integrated Products – Quad, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs

Quad, 12-Bit, 40Msps, 1.8V ADC with
Serial LVDS Outputs
Pin Description (continued)
PIN
NAME
FUNCTION
LVDS Test Pattern Enable Input. Drive LVDSTEST high to enable the output test pattern
64
LVDSTEST (000010111101 MSB→LSB). As with the analog conversion results, the test pattern data is output LSB
first. Drive LVDSTEST low for normal operation.
Reference Input/Output. For internal reference operation (INTREF = GND), the reference output
66
REFIO voltage is 1.24V. For external reference operation (INTREF = AV_DD), apply a stable reference voltage
at REFIO. Bypass to GND with a 0.1µF capacitor.
67
INTREF
Internal/External Reference Mode Select Input. For internal reference mode, connect INTREF directly
to GND. For external reference mode, connect INTREF directly to AV_DD.
—
EP
Exposed Paddle. EP is internally connected to GND. Externally connect EP to GND to achieve
specified performance.
PDALL PD0 PD1 PD2 PD3
AV_DD OV_DD
Functional Diagram
DT SLVS/LVDS
REFIO
INTREF
REFERENCE
SYSTEM
POWER CONTROL
IN0P
T/H
IN0N
IN1P
T/H
IN1N
IN2P
T/H
IN2N
IN3P
T/H
IN3N
CLK
CLOCK
CIRCUITRY
12-BIT
PIPELINE
ADC
12-BIT
PIPELINE
ADC
12-BIT
PIPELINE
ADC
12-BIT
PIPELINE
ADC
PLL
6x
MAX1126
12:1
SERIALIZER
12:1
SERIALIZER
12:1
SERIALIZER
12:1
SERIALIZER
OUTPUT
CONTROL
LVDS/SLVS
OUTPUT
DRIVERS
LVDSTEST
T/B
OUT0P
OUT0N
OUT1P
OUT1N
OUT2P
OUT2N
OUT3P
OUT3N
FRAMEP
FRAMEN
CLKOUTP
CLKOUTN
CV_DD
PLL0 PLL1 PLL2 PLL3
GND
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