LTC3577-4_15 Datasheet, PDF (47/52 Pages) Linear Technology – Highly Integrated Portable Product PMIC

LTC3577-3/LTC3577-4
OPERATION
The LTC3577-3/LTC3577-4 can be used above 20°C, but
the charge current will be reduced below 1A. The charge
current at a given ambient temperature can be approxi-
mated by:
( ) ^P_D
=
110°C – T_A
θ_JA
=
V_OUT – BAT
• I_BAT + P_D(REGS)
Thus:
(^{110°C – T}_A )
I_BAT
=
θ_JA – P_D(REGS)
V_OUT – BAT
Consider the above example with an ambient temperature
of 55°C. The charge current will be reduced to approxi-
mately:
110°C – 55°C _{– 0.3W}
I_BAT =
45°C/W
5V – 3.3V
I_BAT
=
1.22 – 0.3W
1.7V
=
542mA
Printed Circuit Board Layout
When laying out the printed circuit board, the following
list should be followed to ensure proper operation of the
LTC3577-3/LTC3577-4:
1. The Exposed Pad of the package (Pin 45) should connect
directly to a large ground plane to minimize thermal and
electrical impedance.
2. The step-down switching regulator input supply pins
(V_IN12 and V_IN3) and their respective decoupling ca-
pacitors should be kept as short as possible. The GND
side of these capacitors should connect directly to the
ground plane of the part. These capacitors provide the
AC current to the internal power MOSFETs and their driv-
ers. It’s important to minimizing inductance from these
capacitors to the pins of the LTC3577-3/LTC3577-4.
Connect V_IN12 and V_IN3 to V_OUT through a short low
impedance trace.
3. The switching power traces connecting SW1, SW2, and
SW3 to their respective inductors should be minimized
to reduce radiated EMI and parasitic coupling. Due to
the large voltage swing of the switching nodes, sensitive
nodes such as the feedback nodes (FBx, LDOx_FB and
LED_OV) should be kept far away or shielded from the
switching nodes or poor performance could result.
4. Connections between the step-down switching regu-
lator inductors and their respective output capacitors
should be kept as short as possible. The GND side of
the output capacitors should connect directly to the
thermal ground plane of the part.
5. Keep the buck feedback pin traces (FB1, FB2, and FB3)
as short as possible. Minimize any parasitic capacitance
between the feedback traces and any switching node
(i.e. SW1, SW2, SW3, and logic signals). If necessary
shield the feedback nodes with a GND trace.
6. Connections between the LTC3577-3/LTC3577-4 power
path pins (V_BUS and V_OUT) and their respective decou-
pling capacitors should be kept as short as possible. The
GND side of these capacitors should connect directly
to the ground plane of the part.
7. The boost converter switching power trace connect-
ing SW to the inductor should be minimized to reduce
radiated EMI and parasitic coupling. Due to the large
voltage swing of the SW node, sensitive nodes such
as the feedback nodes (FBx, LDOx_FB and LED_OV)
should be kept far away or shielded from this switching
node or poor performance could result.
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