LTC3577-4_15 Datasheet, PDF (38/52 Pages) Linear Technology – Highly Integrated Portable Product PMIC

LTC3577-3/LTC3577-4
OPERATION
I²C Byte Format
Each byte sent to or received from the LTC3577-3/LTC3577-4
must be 8 bits long followed by an extra clock cycle for the
acknowledge bit. The data should be sent to the LTC3577-3/
LTC3577-4 most significant bit (MSB) first.
I²C Acknowledge
The acknowledge signal is used for handshaking between
the master and the slave. When the LTC3577-3/LTC3577-4
are written to (write address), they acknowledge their
write address as well as the subsequent two data bytes.
When they are read from (read address), the LTC3577-3/
LTC3577-4 acknowledge their read address only. The bus
master should acknowledge receipt of information from
the LTC3577-3/LTC3577-4.
An acknowledge (active LOW) generated by the LTC3577-3/
LTC3577-4 let the master know that the latest byte of
information was received. The acknowledge related clock
pulse is generated by the master. The master releases the
SDA line (HIGH) during the acknowledge clock cycle. The
LTC3577-3/LTC3577-4 pull-down the SDA line during the
write acknowledge clock pulse so that it is a stable LOW
during the HIGH period of this clock pulse.
When the LTC3577-3/LTC3577-4 are read from, they re-
lease the SDA line so that the master may acknowledge
receipt of the data. Since the LTC3577-3/LTC3577-4 only
transmit one byte of data, a master not acknowledging the
data sent by the LTC3577-3/LTC3577-4 has no I²C specific
consequence on the operation of the I²C port.
I²C Slave Address
The LTC3577-3/LTC3577-4 respond to a 7-bit address
which has been factory programmed to b’0001001[R/W]’.
The LSB of the address byte, known as the read/write bit,
should be 0 when writing data to the LTC3577-3/LTC3577-4
and 1 when reading data from it. Considering the address
an 8-bit word, then the write address is 0x12 and the read
address is 0x13. The LTC3577-3/LTC3577-4 will acknowl-
edge both its read and write address.
I²C Sub-Addressed Writing
The LTC3577-3/LTC3577-4 have four command registers
for control input. They are accessed by the I²C port via a sub-
addressed writing system.
Each write cycle of the LTC3577-3/LTC3577-4 consists of
exactly three bytes. The first byte is always the LTC3577-3/
LTC3577-4’s write address. The second byte represents the
LTC3577-3/LTC3577-4’s sub-address. The sub address is a
pointer which directs the subsequent data byte within the
LTC3577-3/LTC3577-4. The third byte consists of the data
to be written to the location pointed to by the sub-address.
The LTC3577-3/LTC3577-4 contain control registers at only
four sub-address locations: 0x00, 0x01, 0x02 and 0x03.
Writing to sub-addresses outside the four sub-addresses
listed is not recommended as it can cause data in one of
the four listed sub-addresses to be overwritten.
I²C Bus Write Operation
The master initiates communication with the LTC3577-3/
LTC3577-4 with a START condition and the LTC3577-3/
LTC3577-4’s write address. If the address matches that
of the LTC3577-3/LTC3577-4, the LTC3577-3/LTC3577-4
return an acknowledge. The master should then deliver
the sub-address. Again the LTC3577-3/LTC3577-4 ac-
knowledge and the cycle is repeated for the data byte.
The data byte is transferred to an internal holding latch
upon the return of its acknowledge by the LTC3577-3/
LTC3577-4. This procedure must be repeated for each
sub-address that requires new data. After one or more
cycles of [ADDRESS][SUB-ADDRESS][DATA], the master
may terminate the communication with a STOP condition.
Alternatively, a REPEAT-START condition can be initiated
by the master and another chip on the I²C bus can be
addressed. This cycle can continue indefinitely and the
LTC3577-3/LTC3577-4 will remember the last input of valid
data that it received. Once all chips on the bus have been
addressed and sent valid data, a global STOP can be sent
and the LTC3577-3/LTC3577-4 will update their command
latches with the data that they had received.
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