LTC3577-4_15 Datasheet, PDF (39/52 Pages) Linear Technology – Highly Integrated Portable Product PMIC

LTC3577-3/LTC3577-4
OPERATION
I²C Bus Read Operation
The bus master reads the status of the LTC3577-3/
LTC3577-4 with a START condition followed by the
LTC3577-3/LTC3577-4 read address. If the read address
matches that of the LTC3577-3/LTC3577-4, the LTC3577-3/
LTC3577-4 return an acknowledge. Following the acknowl-
edgement of their read address, the LTC3577-3/LTC3577-4
return one bit of status information for each of the next
8 clock cycles. A STOP command is not required for the
bus read operation.
I²C Input Data
There are 4 bytes of data that can be written to on the
LTC3577-3/LTC3577-4. The bytes are accessed through
the sub-addresses 0x00 to 0x03. At first power applica-
tion (V_BUS, WALL or BAT) all bits default to 0. Addition-
ally all bits are cleared to 0 when DV_CC drops below its
undervoltage lock out or if the pushbutton enters the
power down (PDN) state.
Table 8 shows the first byte of data that can be written to
at sub-address 0x00. This byte of data is referred to as
the “buck control register”.
Table 8. Buck Control Register
BUCK CONTROL
REGISTER
ADDRESS: 00010010
SUB-ADDRESS: 00000000
BIT NAME
FUNCTION
B0 N/A
Not Used—No Effect On Operation
B1 N/A
Not Used—No Effect On Operation
B2 BK1BRST
Buck1 Burst Mode Enable
B3 BK2BRST
Buck2 Burst Mode Enable
B4 BK3BRST
Buck2 Burst Mode Enable
B5 SLEWCTL1
B6 SLEWCTL2
Buck SW Slew Rate: 00 = 1ns,
01 = 2ns, 10 = 4ns, 11 = 8ns
B7 N/A
Not Used—No Effect On Operation
Bits B2, B3, and B4 set the operating modes of the step-
down switching regulators (bucks). Writing a 1 to any of
these three registers will put that respective buck converter
in the high efficiency Burst Mode operation, while a 0 will
enable the low noise pulse-skipping mode of operation.
The B5 and B6 bits adjust the slew rate of all SW pins
together so they all slew at the same rate. It is recom-
mended that the fastest slew rate (B6:B5 = 00) be used
unless EMI is an issue in the application as slower slew
rates cause reduced efficiency.
Table 9 shows the second byte of data that can be written
to at sub-address 0x01. This byte of data is referred to as
the “LED control register”.
Table 9. I²C LED Control Register
LED CONTROL
REGISTER
ADDRESS: 00010010
SUB-ADDRESS: 00000001
BIT NAME
FUNCTION
B0 EN
Enable: 1 = Enable 0 = Off
B1 GR2
B2 GR1
Gradation GR[2:1]: 00 = 15ms, 01 = 460ms,
10 = 930ms, 11 = 1.85 Seconds
B3 MD1
B4 MD2
Mode MD[2:1]: 00 = CC Boost,
10 = PWM Boost; 01 = HV Boost,
B5 PWMC1
B6 PWMC2
PWM CLK PWMC[2:1]: 00 = 8.77kHz,
01 = 4.39kHz, 10 = 2.92kHz, 11 = 2.19kHz
B7 SLEWLED
LED SW Slew Rate: 0/1 = Fast/Slow
Bit B0 enables and disables the LED boost circuitry. Writing
a 1 to B0 enables the LED boost circuitry, while writing a
0 disables the LED boost circuitry.
Bits B1 and B2 are the LED gradation which sets the ramp
up and down time of the LED current when enabled or
disabled. The gradation function allows the LEDs to turn
on/off gradually as opposed to an abrupt step.
Bits B3 and B4 set the operating mode of the LED boost
circuitry. The operating modes are: B4:B3 = 00 LED con-
stant current (CC) boost operation; B4:B3 = 10 LED PWM
boost operation; B4:B3 = 01 fixed high voltage (HV) output
boost operation; B4:B3 = 11, not supported, do not use.
See the “LED Backlight/Boost Operation” section for more
information on the operating modes.
Bits B5 and B6 set the PWM clock speed as shown in
Table 5 of the “LED Backlight/Boost Operation” section.
Bit B7 sets the slew rate of the LED boost SW pin. Setting
B7 to 0 results in the fastest slew rate and provides the
most efficient mode of operation. Setting B7 to 1 should
only be used in cases where EMI due to SW slewing is an
issue as the slower slew rate causes a loss in efficiency.
See the “LED Backlight/Boost Operation” section for more
detailed operating information.
357734fb
39