LTC3577-4_15 Datasheet, PDF (28/52 Pages) Linear Technology – Highly Integrated Portable Product PMIC

LTC3577-3/LTC3577-4
OPERATION
MN1
V1
V2
D2
D1 ^MN2
WALL
LTC3577-3/
LTC3577-4
OVGATE
V_BUS
C1
R1
OVSENS
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Figure 5. Dual Input Overvoltage Protection
USB/WALL
ADAPTER
MP1
MN1
D1
R1
R2
500k
6.2k
V_BUS
C1 _LTC3577-3/
LTC3577-4
OVGATE
OVSENS
D1: 5.6V ZENER
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MP1: Si2323 DS, BVDSS = 20V
V_BUS POSITIVE PROTECTION UP TO BVDSS OF MN1
V_BUS NEGATIVE PROTECTION UP TO BVDSS OF MP1
Figure 6. Dual Polarity Voltage Protection
Dual Input Overvoltage Protection
It is possible to protect both V_BUS and WALL from
overvoltage damage with several additional components,
as shown in Figure 5. Schottky diodes D1 and D2 pass the
larger of V1 and V2 to R1 and OVSENS. If either V1 or V2
exceeds 6V plus V_F(SCHOTTKY), OVGATE will be pulled to
GND and both the WALL and USB inputs will be protected.
Each input is protected up to the drain-source breakdown,
BVDSS, of MN1 and MN2. R1 must also be rated for the
power dissipated during maximum overvoltage. See the
“Overvoltage Protection” section for an explanation of this
calculation. Table 2 shows some NMOS FETs that maybe
suitable for overvoltage protection.
Table 2. Recommended Overvoltage FETs
NMOS FET
BVDSS
R_ON
Si1472DH
30V
82mΩ
Si2302ADS
20V
60mΩ
Si2306BDS
30V
65mΩ
Si2316BDS
30V
80mΩ
IRLML2502
20V
35mΩ
PACKAGE
SC70-6
SOT-23
SOT-23
SOT-23
SOT-23
Reverse Input Voltage Protection
The LTC3577-3/LTC3577-4 can also be easily protected
against the application of reverse voltage as shown in
Figure 6. D1 and R1 are necessary to limit the maximum
VGS seen by MP1 during positive overvoltage events. D1’s
breakdown voltage must be safely below MP1’s BVGS. The
circuit shown in Figure 6 offers forward voltage protection
up to MN1’s BVDSS and reverse voltage protection up to
MP1’s BVDSS.
LOW DROPOUT LINEAR REGULATOR OPERATION
LDO Operation and Voltage Programming
The LTC3577-3/LTC3577-4 contain two 150mA adjustable
output LDO regulators. The first LDO (LDO1) is always
on and will be enabled whenever V_OUT is greater than
V_OUT UVLO. The second LDO (LDO2) is controlled by the
pushbutton and is the first supply to sequence up in re-
sponse to pushbutton application. Both LDOs are disabled
when V_OUT is less than V_OUT UVLO and LDO2 is further
disabled when the pushbutton circuity is in the power
down or power off states. Both LDOs contain a soft-start
function to limit inrush current when enabled. The soft-start
function works by ramping up the LDO reference over a
200μs period (typical) when the LDO is enabled.
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