LTC3577-4_15 Datasheet, PDF (27/52 Pages) Linear Technology – Highly Integrated Portable Product PMIC

LTC3577-3/LTC3577-4
OPERATION
By using a bias resistor, R_NOM, different in value from R25,
the hot and cold trip points can be moved in either direc-
tion. The temperature span will change somewhat due to
the non-linear behavior of the thermistor. The following
equations can be used to easily calculate a new value for
the bias resistor:
R_NOM
=
r_HOT
0.538
• R25
R_NOM
=
r_COLD
3.17
• R25
where r_HOT and r_COLD are the resistance ratios at the
desired hot and cold trip points. Note that these equations
are linked. Therefore, only one of the two trip points can
be chosen, the other is determined by the default ratios
designed in the IC.
Consider an example where a 60°C hot trip point is
desired. From the Vishay Curve 1 R-T characteristics,
r_HOT is 0.2488 at 60°C. Using the above equation, R_NOM
should be set to 46.4k. With this value of R_NOM, the cold
trip point is about 16°C. Notice that the span is now 44°C
rather than the previous 40°C. This is due to the decrease
in temperature gain of the thermistor as absolute tem-
perature increases.
The upper and lower temperature trip points can be inde-
pendently programmed by using an additional bias resistor
as shown in Figure 4. The following formulas can be used
to compute the values of R_NOM and R1:
R_NOM
=
r_COLD – r_HOT
2.714
• R25
R1= 0.536 • R_NOM – r_HOT • R25
For example, to set the trip points to 0°C and 45°C with
a Vishay Curve 1 thermistor choose:
R_NOM
=
3.266 – 0.4368
2.714
• 100k
=
104.2k
the nearest 1% value is 105k.
R1 = 0.536 • 105k – 0.4368 • 100k = 12.6k
the nearest 1% value is 12.7k. The final solution is shown
in Figure 4 and results in an upper trip point of 45°C and
a lower trip point of 0°C.
Overvoltage Protection (OVP)
The LTC3577-3/LTC3577-4 can protect themselves from
the inadvertent application of excessive voltage to V_BUS or
WALL with just two external components: an N-channel
FET and a 6.2k resistor. The maximum safe overvoltage
magnitude will be determined by the choice of the external
NMOS and its associated drain breakdown voltage.
The overvoltage protection module consists of two pins.
The first, OVSENS, is used to measure the externally applied
voltage through an external resistor. The second, OVGATE,
is an output used to drive the gate pin of an external FET.
The voltage at OVSENS will be lower than the OVP input
voltage by (I_OVSENS • 6.2kΩ) due to the OVP circuit’s
quiescent current. The OVP input will be 200mV to 400mV
higher than OVSENS under normal operating conditions.
When OVSENS is below 6V, an internal charge pump will
drive OVGATE to approximately 1.88 • OVSENS. This will
enhance the N-channel FET and provide a low impedance
connection to V_BUS or WALL which will, in turn, power
the LTC3577-3/LTC3577-4. If OVSENS should rise above
6V (6.35V OVP input) due to a fault or use of an incorrect
wall adapter, OVGATE will be pulled to GND, disabling the
external FET to protect downstream circuitry. When the
voltage drops below 6V again, the external FET will be
re-enabled.
In an overvoltage condition, the OVSENS pin will be
clamped at 6V. The external 6.2k resistor must be
sized appropriately to dissipate the resultant power.
For example, a 1/10W 6.2k resistor can have at most
√P_MAX • 6.2k = 24V applied across its terminals. With the
6V at OVSENS, the maximum overvoltage magnitude that
this resistor can withstand is 30V. A 1/4W 6.2k resistor
raises this value to 45V.
The charge pump output on OVGATE has limited output
drive capability. Care must be taken to avoid leakage on
this pin, as it may adversely affect operation.
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