1032E Datasheet, PDF (9/16 Pages) Lattice Semiconductor – In-System Programmable High Density PLD

Specifications ispLSI 1032E
Internal Timing Parameters¹
PARAM. #
DESCRIPTION
-125
-100
UNITS
MIN. MAX. MIN. MAX.
Outputs
tob
tsl
toen
todis
tgoe
Clocks
tgy0
tgy1/2
49 Output Buffer Delay
50 Output Buffer Delay, Slew Limited Adder
51 I/O Cell OE to Output Enabled
52 I/O Cell OE to Output Disabled
53 Global OE
54 Clk Delay, Y0 to Global GLB Clk Line (Ref. clk)
55 Clk Delay, Y1 or Y2 to Global GLB Clk Line
– 1.3
S – ^9.9
– 4.3
N _{– 4.3}
IG – ^2.7
– 2.0 ns
– 10.0 ns
– 5.1 ns
– 5.1 ns
– 3.9 ns
S _{1.4 1.4 1.5 1.5 ns}
DE ^{1.4 1.4 1.5 1.5 ns}
tgcp
56 Clk Delay, Clock GLB to Global GLB Clk Line
0.8
tioy2/3 57 Clk Delay, Y2 or Y3 to I/O Cell Global Clk Line
0.0
W _tiocp
58 Clk Delay, Clk GLB to I/O Cell Global Clk Line
0.8
E _{Global Reset}
N _tgr
59 Global Reset to GLB and I/O Registers
–
FOR ^{1. Internal Timing Parameters are not tested and are for reference only.}
1.8
0.0
1.8
2.8
0.8 1.8 ns
0.0 0.0 ns
0.8 1.8 ns
– 4.3 ns
Table 2-0037A/1032E
ispLSI ^1032EA
USE
9