1032E Datasheet, PDF (11/16 Pages) Lattice Semiconductor – In-System Programmable High Density PLD

Specifications ispLSI 1032E
ispLSI 1032E Timing Model
I/O Cell
GRP
GLB
ORP
I/O Cell
Feedback
Ded. In
#28
#34 Comb 4 PT Bypass
I/O Pin
(Input)
#59
I/O Reg Bypass
#22
Input
D ^Register Q
RST
#23 - 27
Reset
Y1,2,3
GRP4
#30
GRP Loading
Delay
#29, 31 - 33
Clock
Distribution
#55 - 58
Reg 4 PT Bypass
#35
20 PT
XOR Delays
#36 - 38
#59
GLB Reg Bypass
#39
GLB Reg
Delay
D
Q
RST
#40 - 43
Control _RE
PTs _OE
#44 - 46 CK
ORP Bypass
#48
S _ORP
Delay
N _#47
#49, 50
I/O Pin
(Output)
#51, 52
DESIG⁰⁴⁹¹
#54
Y0
GOE 0,1
#53
NEW
Derivations of tsu, th and tco from the Product Term Clock¹
R tsu
= Logic + Reg su - Clock (min)
= (tiobp + tgrp4 + t20ptxor) + (tgsu) – (tiobp + tgrp4 + tptck(min))
O _{= (#22 + #30 + #37) + (#40) – (#22 + #30 + #46)}
F 2.2 ns = (0.3 + 2.0 + 5.0) + (0.1) – (0.3 + 2.0 + 2.9)
th
= Clock (max) + Reg h - Logic
A _{= (tiobp + tgrp4 + tptck(max)) + (tgh) – (tiobp + tgrp4 + t20ptxor)}
E _{= (#22 + #30 + #46) + (#41) - (#22 + #30 + #37)}
2 ^{3.5 ns = (0.3 + 2.0 + 4.0) + (4.5) – (0.3 + 2.0 + 5.0)}
3 _tco
= Clock (max) + Reg co + Output
0 _{= (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob)}
1 _{= (#22 + #30 + #46) + (#42) + (#47 + #49)}
I 10.9 ns = (0.3 + 2.0 + 4.0) + (2.3) + (1.0 + 1.3)
S _{Derivations of tsu, th and tco from the Clock GLB 1}
L _tsu
= Logic + Reg su - Clock (min)
p _{= (tiobp + tgrp4 + t20ptxor) + (tgsu) – (tgy0(min) + tgco + tgcp(min))}
is^{= (#22 + #30 + #37) + (#40) – (#54 + #42 + #56)}
2.9 ns = (0.3 + 2.0 + 5.0) + (0.1) – (1.4 + 2.3 + 0.8)
E ^th
= Clock (max) + Reg h - Logic
= (tgy0(max) + tgco + tgcp(max)) + (tgh) – (tiobp + tgrp4 + t20ptxor)
S _{= (#54 + #42 + #56) + (#41) – (#22 + #30 + #37)}
U ^{2.7 ns = (1.4 + 2.3 + 1.8) + (4.5) – (0.3 + 2.0 + 5.0)}
tco
= Clock (max) + Reg co + Output
= (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob)
= (#54 + #42 + #56) + (#42) + (#47 + #49)
5.5 ns = (1.4 + 2.3 + 1.8) + (2.3) + (1.0 + 1.3)
1. Calculations are based upon timing specifications for the ispLSI 1032E-125.
Table 2-0042a/1032E
11