1032E Datasheet, PDF(2/16 Page) Lattice Semiconductor – In-System Programmable High Density PLD

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1032E Datasheet, PDF (2/16 Pages) Lattice Semiconductor – In-System Programmable High Density PLD

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Functional Block Diagram

Figure 1. ispLSI 1032E Functional Block Diagram

Specifications ispLSI 1032E

RESET

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

Generic

Logic Blocks

(GLBs)

Input Bus

Output Routing Pool (ORP)

D7 D6 D5 D4 D3 D2 D1 D0

NS GOE 1/IN 5

GOE 0/IN 4

IG I/O 47

I/O 46

I/O 45

S I/O 44

EI/O 43

I/O 42

DI/O 41

I/O 5

Global

I/O 40

I/O 6

I/O 7

I/O 8

I/O 9

I/O 10

I/O 11

Routing

Pool

(GRP)

W C2

NEC1

I/O 39

I/O 38

I/O 37

I/O 36

I/O 35

I/O 34

I/O 12

I/O 13

I/O 14

I/O 15

R SDI/IN 0

O MODE/IN 1

F Megablock

A ispEN

B0 B1 B2 B3 B4 B5 B6 B7

Output Routing Pool (ORP)

Input Bus

I/O 33

I/O 32

Clock

Distribution

Network

CLK 0

CLK 1

CLK 2

IOCLK 0

IOCLK 1

032E The device also has 64 I/O cells, each of which is directly

connected to an I/O pin. Each I/O cell can be individually

1 programmed to be a combinatorial input, registered in-

I put, latched input, output or bi-directional

S I/O pin with 3-state control. The signal levels are TTL

compatible voltages and the output drivers can source 4

L mA or sink 8 mA. Each output can be programmed

p independently for fast or slow output slew rate to mini-

is mize overall output switching noise.

The GRP has, as its inputs, the outputs from all of the

GLBs and all of the inputs from the bi-directional I/O cells.

All of these signals are made available to the inputs of the

GLBs. Delays through the GRP have been equalized to

minimize timing skew.

Clocks in the ispLSI 1032E device are selected using the

Clock Distribution Network. Four dedicated clock pins

(Y0, Y1, Y2 and Y3) are brought into the distribution

Eight GLBs, 16 I/O cells, two dedicated inputs and one

E ORP are connected together to make a Megablock (see

S Figure 1). The outputs of the eight GLBs are connected

U to a set of 16 universal I/O cells by the ORP. Each ispLSI

network, and five clock outputs (CLK 0, CLK 1, CLK 2,

IOCLK 0 and IOCLK 1) are provided to route clocks to the

GLBs and I/O cells. The Clock Distribution Network can

also be driven from a special clock GLB (C0 on the ispLSI

1032E device). The logic of this GLB allows the user to

1032E device contains four Megablocks.

create an internal clock from a combination of internal

signals within the device.

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