1032E Datasheet, PDF (8/16 Pages) Lattice Semiconductor – In-System Programmable High Density PLD

Specifications ispLSI 1032E
Internal Timing Parameters¹
PARAM. # ²
DESCRIPTION
-90
-80
-70
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
Inputs
tiobp 22 I/O Register Bypass
tiolat 23 I/O Latch Delay
tiosu 24 I/O Register Setup Time before Clock
tioh
25 I/O Register Hold Time after Clock
tioco 26 I/O Register Clock to Out Delay
tior
27 I/O Register Reset to Out Delay
tdin
28 Dedicated Input Delay
GRP
–
–
3.5
0.0
–
–
–
0.3
2.3
–
–
5.0
5.0
2.6
– 0.3 – 0.3 ns
S _{– 2.7 – 3.3 ns}
N _{3.5 – 4.0 – ns}
0.0 – 0.0 – ns
IG _{– 5.4 – 6.1 ns}
S _{– 5.4 – 6.0 ns}
DE ^{– 2.8 – 2.8 ns}
tgrp1
tgrp4
tgrp8
tgrp16
29 GRP Delay, 1 GLB Load
30 GRP Delay, 4 GLB Loads
31 GRP Delay, 8 GLB Loads
32 GRP Delay, 16 GLB Loads
– 2.1 –
– 2.3 –
W _{– 2.6 –}
NE^{– 3.2 –}
2.2
2.5
2.8
3.5
–
–
–
–
2.5
2.5
3.2
4.0
ns
ns
ns
ns
tgrp32
GLB
t4ptbpc
t4ptbpr
33 GRP Delay, 32 GLB Loads
R _{34 4 Prod.Term Bypass Path Delay (Combinatorial)}
FO ^{35 4 Prod. Term Bypass Path Delay (Registered)}
–
–
–
4.4
5.7
6.1
–
–
–
4.8
7.1
6.7
–
–
–
5.6
8.8
7.2
ns
ns
ns
t1ptxor 36 1 Prod.Term/XOR Path Delay
A ^{t20ptxor 37 20 Prod. Term/XOR Path Delay}
txoradj 38 XOR Adjacent Path Delay ³
E _{tgbp 39 GLB Register Bypass Delay}
32 ^tgsu
40 GLB Register Setup Time before Clock
0 ^tgh
41 GLB Register Hold Time after Clock
1 ^tgco
42 GLB Register Clock to Output Delay
I tgro
43 GLB Register Reset to Output Delay
S ^{tptre 44 GLB Prod.Term Reset to Register Delay}
L ^{tptoe 45 GLB Prod. Term Output Enable to I/O Cell Delay}
p ^tptck
46 GLB Prod. Term Clock Delay
is ^ORP
torp
47 ORP Delay
torpbp 48 ORP Bypass Delay
E _{1. Internal Timing Parameters are not tested and are for reference only.}
S _{2. Refer to Timing Model in this data sheet for further details.}
U ^{3. The XOR adjacent path can only be used by hard macros.}
– 5.6 – 6.6 – 8.3 ns
– 6.8 – 7.8 – 8.7 ns
– 7.1 – 8.2 – 9.2 ns
– 0.4 – 1.3 – 1.6 ns
0.2 – 0.5 – 0.5 – ns
6.8 – 7.9 – 8.8 – ns
– 2.9 – 2.9 – 2.9 ns
– 6.3 – 6.4 – 6.8 ns
– 5.1 – 5.5 – 5.8 ns
– 7.1 – 8.0 – 9.0 ns
4.1 5.3 4.5 5.8 4.8 6.2 ns
– 1.0 – 1.0 – 1.0 ns
– 0.0 – 0.0 – 0.0 ns
Table 2-0036B/1032E
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