1032E Datasheet, PDF (7/16 Pages) Lattice Semiconductor – In-System Programmable High Density PLD

Specifications ispLSI 1032E
Internal Timing Parameters¹
PARAM. # ²
DESCRIPTION
-125
-100
UNITS
MIN. MAX. MIN. MAX.
Inputs
tiobp
tiolat
tiosu
tioh
tioco
tior
tdin
GRP
22 I/O Register Bypass
23 I/O Latch Delay
24 I/O Register Setup Time before Clock
25 I/O Register Hold Time after Clock
26 I/O Register Clock to Out Delay
27 I/O Register Reset to Out Delay
28 Dedicated Input Delay
– 0.3 – 0.3 ns
S – 1.9 – 2.3 ns
N ^{3.0 – 3.5 – ns}
0.0 – 0.0 – ns
IG – 4.6 – 5.0 ns
S ^{– 4.6 – 5.0 ns}
DE ^{– 2.3 – 2.7 ns}
tgrp1 29 GRP Delay, 1 GLB Load
–
tgrp4 30 GRP Delay, 4 GLB Loads
–
W _{tgrp8 31 GRP Delay, 8 GLB Loads}
–
E _{tgrp16 32 GRP Delay, 16 GLB Loads}
–
N _{tgrp32 33 GRP Delay, 32 GLB Loads}
–
GLB
R _{t4ptbpc 34 4 Prod.Term Bypass Path Delay (Combinatorial)}
–
O _{t4ptbpr 35 4 Prod. Term Bypass Path Delay (Registered)}
–
F _{t1ptxor 36 1 Prod.Term/XOR Path Delay}
–
t20ptxor 37 20 Prod. Term/XOR Path Delay
–
A _{txoradj 38 XOR Adjacent Path Delay 3}
–
E _{tgbp 39 GLB Register Bypass Delay}
–
2 _tgsu
40 GLB Register Setup Time before Clock
0.1
3 _tgh
41 GLB Register Hold Time after Clock
4.5
0 _tgco
42 GLB Register Clock to Output Delay
–
1 _tgro
43 GLB Register Reset to Output Delay
–
I _{tptre 44 GLB Prod.Term Reset to Register Delay}
–
S _{tptoe 45 GLB Prod. Term Output Enable to I/O Cell Delay}
–
L _tptck
46 GLB Prod. Term Clock Delay
2.9
p _ORP
is torp
47 ORP Delay
–
torpbp 48 ORP Bypass Delay
–
E _{1. Internal Timing Parameters are not tested and are for reference only.}
S 2. Refer to Timing Model in this data sheet for further details.
U ^{3. The XOR adjacent path can only be used by hard macros.}
1.8
2.0
2.3
2.8
3.8
3.9
4.0
3.6
5.0
5.0
0.4
–
–
2.3
4.9
3.9
5.4
4.0
1.0
0.0
– 1.9 ns
– 2.4 ns
– 2.4 ns
– 3.0 ns
– 4.2 ns
– 5.3 ns
– 5.3 ns
– 4.6 ns
– 5.8 ns
– 6.3 ns
– 1.0 ns
0.5 – ns
5.8 – ns
– 2.5 ns
– 6.2 ns
– 4.5 ns
– 7.2 ns
3.5 4.7 ns
– 1.0 ns
– 0.0 ns
Table 2-0036A/1032E
7