1032E Datasheet, PDF (10/16 Pages) Lattice Semiconductor – In-System Programmable High Density PLD

Specifications ispLSI 1032E
Internal Timing Parameters¹
PARAM. #
DESCRIPTION
-90
-80
-70
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
Outputs
tob
tsl
toen
todis
tgoe
Clocks
tgy0
tgy1/2
49 Output Buffer Delay
50 Output Buffer Delay, Slew Limited Adder
51 I/O Cell OE to Output Enabled
52 I/O Cell OE to Output Disabled
53 Global OE
54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
55 Clock Delay, Y1 or Y2 to Global GLB Clock Line
– 1.7
– 10.0
– 5.3
– 5.3
– 3.7
1.4 1.4
2.4 2.9
– 2.1 – 2.6 ns
S ^{– 10.0 – 10.0 ns}
– 5.7 – 6.2 ns
N _{– 5.7 – 6.2 ns}
IG ^{– 4.3 – 5.8 ns}
S _{1.5 1.5 1.5 1.5 ns}
DE ^{2.6 3.1 1.5 1.5 ns}
tgcp
56 Clock Delay, Clock GLB to Global GLB Clock Line
tioy2/3 57 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line
tiocp
58 Clock Delay, Clock GLB to I/O Cell Global Clock Line
Global Reset
tgr
59 Global Reset to GLB and I/O Registers
0.8 1.8 0.8
0.0 0.0 0.0
W _{0.8 1.8 0.8}
NE– 4.5 –
1.8
0.0
1.8
4.5
0.8
0.0
0.8
–
1.8
0.0
1.8
4.6
ns
ns
ns
ns
FOR ^{1. Internal Timing Parameters are not tested and are for reference only.}
Table 2-0037B/1032E
ispLSI ^1032EA
USE
10