1032E Datasheet, PDF (13/16 Pages) Lattice Semiconductor – In-System Programmable High Density PLD

Specifications ispLSI 1032E
Pin Description
NAME
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
I/O 32 - I/O 35
I/O 36 - I/O 39
I/O 40 - I/O 43
I/O 44 - I/O 47
I/O 48 - I/O 51
I/O 52 - I/O 55
I/O 56 - I/O 59
I/O 60 - I/O 63
GOE 0/IN 4³
GOE 1/IN 5³
IN 6, IN 7
ispEN
SDI/IN 0²
MODE/IN 1²
SDO/IN 2²
SCLK/IN 3²
RESET
Y0
Y1
Y2
Y3
E _GND
S_VCC
U_NC1
PLCC PIN
NUMBERS
TQFP PIN
NUMBERS
DESCRIPTION
26, 27, 28, 29, 17, 18, 19, 20, Input/Output Pins - These are the general purpose I/O pins used by the logic
30, 31, 32, 33, 21, 22, 23, 28, array.
34, 35, 36, 37, 29, 30, 31, 32,
38,
45,
49,
53,
57,
68,
72,
76,
80,
3,
7,
11,
15,
67
39,
46,
50,
54,
58,
69,
73,
77,
81,
4,
8,
12,
16,
40, 41,
47, 48,
51, 52,
55, 56,
59, 60,
70, 71,
74, 75,
78, 79,
82, 83,
5, 6,
9, 10,
13, 14,
17, 18
33,
40,
44,
48,
56,
67,
71,
79,
83,
90,
94,
98,
6,
66
34,
41,
45,
53,
57,
68,
72,
80,
84,
91,
95,
3,
7,
35,
42,
46,
54,
58,
69,
73,
81,
85,
92,
96,
4,
8,
36,
43,
47,
55,
59,
70,
78,
82,
86,
93,
97,
5,
9
ESIGNS _{This is a dual function pin. It can be used either as Global Output Enable for}
D all I/O cells or it can be used as a dedicated input pin.
84
2, 19
87
89, 10
This is a dual function pin. It can be used either as Global Output Enable for
all I/O cells or it can be used as a dedicated input pin.
NEW ^{Dedicated input pins to the device.}
23
25
14
16
Input - Dedicated in-system programming enable input pin. This pin is
brought low to enable the programming mode. The MODE, SDI, SDO and
SCLK options become active.
R _{Input - This pin performs two functions. When ispEN is logic low, it functions}
as an input pin to load programming data into the device. SDI/IN 0 is also
O _{used as one of the two control pins for the isp state machine. It is a}
F ^{dedicated input pin when ispEN is logic high.}
42
37
Input - This pin performs two functions. When ispEN is logic low, it functions
as pin to control the operation of the isp state machine. It is a dedicated
input pin when ispEN is logic high.
A ₄₄
39
Output/Input - This pin performs two functions. When ispEN is logic low, it
E^{functions as an output pin to read serial shift register data. It is a dedicated}
input pin when ispEN is logic high.
2 ₆₁
60
Input - This pin performs two functions. When ispEN is logic low, it functions
as a clock pin for the Serial Shift Register. It is a dedicated input pin when
3 _{ispEN is logic high.}
0 ₂₄
15
Active Low (0) Reset pin which resets all of the GLB and I/O registers in the
1 device.
I ²⁰
11
Dedicated Clock input. This clock input is connected to one of the clock
inputs of all of the GLBs on the device.
S 66
65
Dedicated Clock input. This clock input is brought into the clock distribution
network, and can optionally be routed to any GLB on the device.
L ₆₃
62
Dedicated Clock input. This clock input is brought into the clock distribution
p _{network, and can optionally be routed to any GLB and/or any I/O cell on the}
device.
is₆₂
61
Dedicated Clock input. This clock input is brought into the clock distribution
network, and can optionally be routed to any I/O cell on the device.
1, 22, 43, 64
21, 65
13, 38, 63, 88 ^{Ground (GND)}
12, 64
Vcc
1, 2,
26, 27,
51, 52,
76, 77,
24, 25, No connect.
49, 50,
74, 75,
99, 100
1. NC pins are not to be connected to any active signals, Vcc or GND.
2. Pins have dual function capability.
3. Pins have dual function capability which is software selectable.
Table 2-0002A/1032E
13