1032E Datasheet, PDF (12/16 Pages) Lattice Semiconductor – In-System Programmable High Density PLD

Specifications ispLSI 1032E
Maximum GRP Delay vs GLB Loads
6.0
ispLSI 1032E-70
5.0
ispLSI 1032E-80
4.0
3.0
2.0
1.0
ispLSI 1032E-90/100
DESIGNS ^{ispLSI 1032E-125}
Power Consumption
14
8
16
GLB Load
32
NEW ^{GRP/GLB/1032E}
Power consumption in the ispLSI 1032E device depends
on two primary factors: the speed at which the device is
operating, and the number of product terms used. Figure
3 shows the relationship between power and operating
FOR ^speed.
Figure 3. Typical Device Power Consumption vs fmax
A ₃₅₀
E ₃₀₀
ispLSI 1032E
32 250
0 ₂₀₀
I ^{1 150}
S 100
L₀
20
40 60
80 100 125
p _{fmax (MHz)}
is Notes: Configuration of eight 16-bit counters
Typical current at 5V, 25°C
E I _CC can be estimated for the ispLSI 1032E using the following equation:
S I _CC(mA) = 15 + (# of PTs _* 0.59) + (# of nets _* Max freq _* 0.0078)
U Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The I_CC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of four GLB
loads on average exists. These values are for estimates only. Since the value of I _CC is sensitive to operating
conditions and the program in the device, the actual I _CC should be verified.
0127/1032E
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