PALCE16V8 Datasheet, PDF (4/32 Pages) Advanced Micro Devices – EE CMOS 20-Pin Universal Programmable Array Logic

Registered Output Configuration
The control bit settings are SG0 = 0, SG1 = 1 and SL0_x = 0. There is only one registered
configuration. All eight product terms are available as inputs to the OR gate. Data polarity is
determined by SL1_x. The flip-flop is loaded on the LOW-to-HIGH transition of CLK. The feedback
path is from Q on the register. The output buffer is enabled by OE.
Combinatorial Configurations
The PALCE16V8 has three combinatorial output configurations: dedicated output in a non-
registered device, I/O in a non-registered device and I/O in a registered device.
Dedicated Output in a Non-Registered Device
The control bit settings are SG0 = 1, SG1 = 0 and SL0_x = 0. All eight product terms are available
to the OR gate. Although the macrocell is a dedicated output, the feedback is used, with the
R exception of pins 15 and 16. Pins 15 and 16 do not use feedback in this mode. Because CLK
and OE are not used in a non-registered device, pins 1 and 11 are available as input signals. Pin
FO ^{1 will use the feedback path of MC7, and pin 11 will use the feedback path of MC0.}
Combinatorial I/O in a Non-Registered Device
S _{The control bit settings are SG0 = 1, SG1 = 1, and SL0x = 1. Only seven product terms are}
E _{available to the OR gate. The eighth product term is used to enable the output buffer. The signal}
IC ^{S at the I/O pin is fed back to the AND array via the feedback multiplexer. This allows the pin to}
N _{be used as an input.}
EV ^{IG Because CLK and OE are not used in a non-registered device, pins 1 and 11 are available as}
inputs. Pin 1 will use the feedback path of MC₇, and pin 11 will use the feedback path of MC₀.
D ^S _{Combinatorial I/O in a Registered Device}
L _{DE The control bit settings are SG0 = 0, SG1 = 1 and SL0x = 1. Only seven product terms are available}
A ^{to the OR gate. The eighth product term is used as the output enable. The feedback signal is the}
corresponding I/O signal.
G ^W _{Dedicated Input Configuration}
SE ^{NE The control bit settings are SG0 = 1, SG1 = 0 and SL0x = 1. The output buffer is disabled. Except}
for MC₀ and MC₇, the feedback signal is an adjacent I/O. For MC₀ and MC₇, the feedback signals
U ^{are pins 1 and 11. These configurations are summarized in Table 1 and illustrated in Figure 2.}
Table 1. Macrocell Configuration
Cell
SG0 SG1 SL0_X Configuration
Devices
Emulated
Cell
SG0 SG1 SL0_X Configuration
Devices
Emulated
Device Uses Registers
Device Uses No Registers
0
1
0
Registered Output
PAL16R8, 16R6,
16R4
1
0
0
Combinatorial
Output
PAL10H8, 12H6,
14H4, 16H2, 10L8,
12L6, 14L4, 16L2
0
1
1
Combinatorial
I/O
PAL16R6, 16R4
1
0
1
PAL12H6, 14H4,
Input
16H2, 12L6, 14L4,
16L2
1
1
1
Combinatorial
I/O
PAL16L8
4
PALCE16V8 and PALCE16V8Z Families