PALCE16V8 Datasheet, PDF (3/32 Pages) Advanced Micro Devices – EE CMOS 20-Pin Universal Programmable Array Logic

Alternatively, the device can be programmed as a PALCE16V8. Here the user must use the
PALCE16V8 device code. This option allows full utilization of the macrocell.
To
Adjacent
11
Macrocell
11
OE _{1 0}
0X
V_CC
00
01
10
SL0_X
R ^SG1
11
0X
DQ
10
FO ^SL1X
CLK
Q
ICESNS _{*In macrocells MC0 and MC7, SG1 is replaced by SG0 on the feedback multiplexer.}
10
11
0X
*SG1
SL0_X
EV ^{IG Figure 1. PALCE16V8 Macrocell}
I/O_X
From
Adjacent
Pin
16493E-2
D _{ES CONFIGURATION OPTIONS}
L _{D Each macrocell can be configured as one of the following: registered output, combinatorial}
A output, combinatorial I/O, or dedicated input. In the registered output configuration, the output
buffer is enabled by the OE pin. In the combinatorial configuration, the buffer is either controlled
G ^W _{by a product term or always enabled. In the dedicated input configuration, it is always disabled.}
E ^{E With the exception of MC}0 ^{and MC}7^{, a macrocell configured as a dedicated input derives the}
S ^{N input signal from an adjacent I/O. MC0 derives its input from pin 11 (OE) and MC7 from pin 1}
U ^(CLK).
The macrocell configurations are controlled by the configuration control word. It contains 2
global bits (SG0 and SG1) and 16 local bits (SL0₀ through SL0₇ and SL1₀ through SL1₇). SG0
determines whether registers will be allowed. SG1 determines whether the PALCE16V8 will
emulate a PAL16R8 family or a PAL10H8 family device. Within each macrocell, SL0_x, in
conjunction with SG1, selects the configuration of the macrocell, and SL1_x sets the output as
either active low or active high for the individual macrocell.
The configuration bits work by acting as control inputs for the multiplexers in the macrocell.
There are four multiplexers: a product term input, an enable select, an output select, and a
feedback select multiplexer. SG1 and SL0_x are the control signals for all four multiplexers. In
MC₀ and MC₇, SG0 replaces SG1 on the feedback multiplexer. This accommodates CLK being
the adjacent pin for MC₇ and OE the adjacent pin for MC₀.
PALCE16V8 and PALCE16V8Z Families
3