PALCE16V8 Datasheet, PDF (1/32 Pages) Advanced Micro Devices – EE CMOS 20-Pin Universal Programmable Array Logic

PALCE16V8 COM’L:H-5/7/10/15/25, Q-10/15/25 IND:H-10/15/25, Q-20/25
PALCE16V8Z COM’L:-25
IND:-12/15/25
PALCE16V8 and PALCE16V8Z Families
EE CMOS (Zero-Power) 20-Pin Universal
Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
x Pin and function compatible with all 20-pin PAL^® devices
x Electrically erasable CMOS technology provides reconfigurable logic and full testability
x High-speed CMOS technology
— 5-ns propagation delay for “-5” version
— 7.5-ns propagation delay for “-7” version
x Direct plug-in replacement for the PAL16R8 series
x Outputs programmable as registered or combinatorial in any combination
x Peripheral Component Interconnect (PCI) compliant
x Programmable output polarity
x Programmable enable/disable control
x Preloadable output registers for testability
x Automatic register reset on power up
FOR
x Cost-effective 20-pin plastic DIP, PLCC, and SOIC packages
S x Extensive third-party software and programmer support
E ^{x Fully tested for 100% programming and functional yields and high reliability}
S _{x 5-ns version utilizes a split leadframe for improved performance}
EVIC ^{IGN GENERAL DESCRIPTION}
D ^{S The PALCE16V8 is an advanced PAL device built with low-power, high-speed, electrically-}
erasable CMOS technology. It is functionally compatible with all 20-pin GAL devices. The
E _{macrocells provide a universal device architecture. The PALCE16V8 will directly replace the}
L _{D PAL16R8, with the exception of the PAL16C1.}
A _{The PALCE16V8Z provides zero standby power and high speed. At 30-µA maximum standby}
G ^W _{current, the PALCE16V8Z allows battery-powered operation for an extended period.}
E ^{E The PALCE16V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to}
S ^{N implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic}
U ^{can always be reduced to sum-of-products form, taking advantage of the very wide input gates}
available in PAL devices. The equations are programmed into the device through floating-gate
cells in the AND logic array that can be erased electrically.
The fixed OR array allows up to eight data product terms per output for logic functions. The
sum of these products feeds the output macrocell. Each macrocell can be programmed as
registered or combinatorial with an active-high or active-low output. The output configuration
is determined by two global bits and one local bit controlling four multiplexers in each
macrocell.
Publication# 16493 Rev: F
Amendment/0
Issue Date: September 2000