ISL6551IREC Datasheet, PDF (9/23 Pages) Intersil Corporation – ZVS Full Bridge PWM Controller

Shutdown Timing Diagrams
LATSD
ISL6551IREC
LATCH CANNOT BE RESET BY ON/OFF
C
ON/OFF
VDD
ILIM_OUT
A
PKILIM > BGREF
B
PKILIM < BGREF
D
E
VDD_ON
LATCH RESET BY
REMOVING VDD
F
VDD_OFF
SOFT-START
DRIVER
ENABLE
SOFT-START
SHUTDOWN
FAULT
FAULT
OFF
OVERCURRENT LATCHED OFF/ON
LATCH
RESET
UNDERVOLTAGE
LOCKOUT
Shutdown Timing Descriptions
A (ON/OFF)
When the ON/OFF is pulled low, the soft-start capacitor is
discharged and all the drivers are disabled. When the
ON/OFF is released without a fault condition, a soft-start is
initiated.
B (OVERCURRENT)
If the output of the converter is over loaded, i.e., the PKILIM
is above the bandgap reference voltage (BGREF), the soft-
start capacitor is discharged very quickly and all the drivers
are turned off. Thereafter, the soft-start capacitor is charged
slowly, and discharged quickly if the output is overloaded
again. The soft-start will remain in hiccup mode as long as
the overload conditions persist. Once the overload is
removed, the soft-start capacitor is charged up and the
converter is then back to normal operation.
C (LATCHING SHUTDOWN)
The IC is latched off completely as the LATSD pin is pulled
high, and the soft-start capacitor is reset.
D (ON/OFF)
The latch cannot be reset by the ON/OFF.
9
E (LATCH RESET)
The latch is reset by removing the VDD. The soft-start
capacitor starts to be charged after VDD increases above
the turn-on threshold VDD_ON.
F (VDD UVLO)
The IC is turned off when the VDD is below the turn-off
threshold VDD_OFF. Hysteresis VDD_HYS is incorporated in
the undervoltage lockout (UVLO) circuit.
Block/Pin Functional Descriptions
Detailed descriptions of each individual block in the
functional block diagram on page 3 are included in this
section. Application information and design considerations
for each pin and/or each block are also included.
IC Bias Power (VDD, VDDP1, VDDP2)
• The IC is powered from a 12V ±10% supply.
• VDD supplies power to both the digital and analog circuits
and should be bypassed directly to the VSS pin with an
0.1µF low ESR ceramic capacitor.
FN6762.0
September 2, 2008