ISL6551IREC Datasheet, PDF (12/23 Pages) Intersil Corporation – ZVS Full Bridge PWM Controller

ISL6551IREC
CSS
400mV
+
(SEE FIG. 9)
-
SSL
(TO
VDD
BLANKING
CIRCUIT)
Iss
R_CSS
SHUTDOWN
ERROR AMP
EAI
(–)
EANI
(+)
EAO
FIGURE 5. SIMPLIFIED CLAMP/SOFT-START
Peak Current Limit (PKILIM)
• When the voltage at PKILIM exceeds the BGREF voltage,
the gate pulses are terminated and held low until the next
clock cycle. The peak current limit circuit has a high-speed
loop with propagation delay IpkDel. Peak current shutdown
initiates a soft-start sequence.
• The peak current shutdown threshold is usually set slightly
higher than the normal cycle-by-cycle PWM peak current
limit (Vclamp) and therefore will normally only be activated in
a short-circuit condition. The limit can be set with a resistor
divider from the ISENSE pin. The resistor divider relationship
is defined in Equation 7.
• In general, the trip point is a little smaller than the BGREF
due to the noise and/or ripple at the BGREF.
R_UP
R_DOWN
ISENSE
PKILIM
FIGURE 6. PEAK CURRENT LIMIT SET CIRCUIT
----------R-----d---o----w-----n-----------
Rdown + Rup
=
I---S----E---B--N---G-S----R-E----E(^{---m-F----a----x----})
(EQ. 7)
Latching Shutdown (LATSD)
• A high TTL level on LATSD latches the IC off. The IC goes
into a low power mode and is reset only after the power at the
VDD pin is removed completely. The ON/OFF cannot reset
the latch.
• This pin can be used to latch the power supply off on output
overvoltage or other undesired conditions.
ON/OFF (ON/OFF)
• A high standard TTL input (safe also for VDD level) signals
the controller to turn on. A low TTL input turns off the
controller and terminates all drive signals including the SYNC
outputs. The soft-start is reset.
• This pin is a non-latching input and can accept an enable
command when monitoring the input voltage and the thermal
condition of a converter.
Resonant Delay (R_RESDLY)
• A resistor tied between R_RESDLY and VSS determines the
delay that is required to turn on a lower FET after its
corresponding upper FET is turned off. This is the resonant
delay, which can be estimated with Equation 8.
t_RESDLY = 4.01 x R_RESDLY/kΩ + 13 (ns)
(EQ. 8)
• Figure 7 illustrates the relationship of the value of the resistor
(R_RESDLY) and the resonant delay (t_RESDLY). The
percentages in the figure are the tolerances at the two end
points of the curve.
500
+18%
450
-24%
400
350
300
250
200
150
100
50
0
+37%
+4%
20
40
60
80
R_RESDLY (kΩ)
100 120
FIGURE 7. R_RESDLY vs RESDLY
Leading Edge Blanking (R_LEB)
• In current mode control, the sensed switch (FET) current is
processed in the Ramp Adjust and LEB circuits and then
compared to a control signal (EAO voltage). Spikes, due to
parasitic elements in the bridge circuit, would falsely trigger
the comparator generating the PWM signal. To prevent false
triggering, the leading edge of the sensed current signal is
blanked out by a period that can be programmed with the
R_LEB resistor. Internal switches gate the analog input to the
PWM comparator, implementing the blanking function that
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FN6762.0
September 2, 2008