ISL6551IREC Datasheet, PDF (5/23 Pages) Intersil Corporation – ZVS Full Bridge PWM Controller

ISL6551IREC
Absolute Maximum Ratings
Supply Voltage VDD, VDDP1, VDDP2 . . . . . . . . . . . . . . -0.3 to 16V
Enable Inputs (ON/OFF, LATSD) . . . . . . . . . . . . . . . . . . . . . . . . VDD
Power Good Sink Current (I_DCOK) . . . . . . . . . . . . . . . . . . . . . . 5mA
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . 0°C to +85°C
Supply Voltage Range, VDD . . . . . . . . . . . . . . . . . . . 10.8V to 13.2V
Supply Voltage Range, VDDP1 and VDDP2 . . . . . . . . . . . . . <13.2V
Maximum Operating Junction Temperature . . . . . . . . . . . . . . +125°C
Thermal Information
Thermal Resistance
θ_JA (°C/W) θ_JC (°C/W)
QFN Package (Notes 1, 2). . . . . . . . . .
30
2.5
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θ_JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379 for details.
2. For θ_JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
These specifications apply for VDD = VDDP = 12V and T_A = 0°C to +85°C, Unless Otherwise Stated.
Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature
limits established by characterization and are not production tested.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
SUPPLY (VDD, VDDP1, VDDP2)
Supply Voltage
VDD
10.8 12.0 13.2 V
Bias Current from VDD
IDD VDD = 12V (not including drivers current at VDDP) 5 13 18 mA
Total Current from VDD and VDDP
ICC VDD = VDDP = 12V, F = 1MHz, 1.6nF Load
60
mA
UNDERVOLTAGE LOCKOUT (UVLO)
Start Threshold
Stop Threshold
Hysteresis
CLOCK GENERATOR (CT, RD)
VDD_ON
VDD_OFF
VDD_HYS
9.2 9.6 9.9 V
8.03 8.6 8.87 V
0.3 1 1.9 V
Frequency Range
F
VDD = 12V (Figure 1)
100
1000 kHz
Dead Time Pulse Width (Note 3)
DT
VDD = 12V (Figure 3)
50
1000 ns
BANDGAP REFERENCE (BGREF)
Bandgap Reference Voltage
VREF VDD = 12V, 399kΩ pull-up, 0.1µF, after trimming 1.250 1.263 1.280 V
Bandgap Reference Output Current
IREF
VDD = 12V, see “Block/Pin Functional
Descriptions” on page 9 for details
100 µA
PWM DELAYS (Note 3)
LOW1, 2 delay “Rising”
LOWR With respect to RESDLY rising
5
ns
LOW1, 2 delay “Falling”
LOWF Compare Delay @ Verror = Vramp
44
ns
SYNC1, 2 delay “Falling”
SYNCF With respect to RESDLY falling and with 20pF load
18
ns
SYNC1, 2 delay “Rising”
SYNCR With respect to CLK rising and with 20pF load
20
ns
ERROR AMPLIFIER (EANI, EAI, EAO) (Note 3)
Unity Gain Bandwidth
UGBW
10
MHz
DC Gain
DCG
79
dB
Maximum Offset Error Voltage
Vos
3.1 mV
Input Common Mode Range
Vcm VDD = 12V
0.4
9
V
Common Mode Rejection Ratio
CMMR
82
dB
Power Supply Rejection Ratio
PSSR 1mA load
95
dB
Maximum Output Source Current
ISRC
2
mA
5
FN6762.0
September 2, 2008