ISL6551IREC Datasheet, PDF (14/23 Pages) Intersil Corporation – ZVS Full Bridge PWM Controller

ISL6551IREC
EAO
+
-
30mV
- ADJ
+
OTA
CS_COMP
0.1µF
1k
EANI
(+)
SHARE
OUTPUT
REFERENCE
30k
FIGURE 10. SIMPLIFIED CURRENT SHARE CIRCUIT
SYNC Outputs (SYNC1, SYNC2)
• SYNC1 and SYNC2 are the gate control signals for the
output synchronous rectifiers. They are biased by VDD
and are capable of driving capacitive loads up to 20pF at
1MHz clock frequency (500kHz switching frequency).
These outputs are turned off sooner than the turn-off at
UPPER1 and UPPER2 by the clock dead time, DT.
• Inverting both SYNC signals or both LOWER signals is
another possible way to control the drivers of the
synchronous rectifiers. When using these drive schemes,
the user should understand the issues that might occur in
his/her applications, especially the impacts on current
share operation and light load operation. Refer to
application note AN1002 for more details.
• External high current drivers controlled by the
synchronous signals are required to drive the
synchronous rectifiers. A pulse transformer is required to
pass the drive signals to the secondary side if the IC is
used in a primary control system.
between CS_COMP and VSS pins to achieve a low
current sharing loop bandwidth (100Hz to 500Hz).
Power-Good (DCOK)
• DCOK pin is an open drain output capable of sinking 5mA.
It is low when the output voltage is within the UVOV
window. The static regulation limit is ±3%, while the ±5% is
the dynamic regulation limit. It indicates power-good when
the EAI is within -3% to +5% on the rising edge and within
+3% to -5% on the falling edge, as shown in Figure 11.
EAI
+5%
+3%
EANI
-3%
-5%
Share Support (SHARE, CS_COMP)
• The unit with the highest reference is the master. Other
units, as slaves, adjust their references via a source resistor
to match the master reference sharing the load current. The
source resistor is typically 1kΩ connecting the EANI pin and
the OUTPUT REFERENCE (external reference or
BGREF), as shown in Figure 10. The share bus represents
a 30kΩ resistive load per unit, up to 10 units.
• The output (ADJ) of “Operational Transconductance
Amplifier (OTA)” can only pull high and it is floating while in
master mode. This ensures that no current is sourced to the
OUTPUT REFERENCE when the IC is working by itself.
• The slave units attempt to drive their error amplifier
voltage to be within a pre-determined offset (30mV typical)
of the master error voltage (the share bus). The current-
share error is nominally (30mV/EAO)*100% assuming no
other source of error. With a 2.5V full load error amp
voltage, the current-share error at full load would be -1.2%
(slaves relative to master).
• The bandwidth of the current sharing loop should be much
lower than that of the voltage loop to eliminate noise pick-
up and interactions between the voltage regulation loop
and the current loop. A 0.1µF capacitor is recommended
DCOK
FAULT
FIGURE 11. UNDERVOLTAGE-OVERVOLTAGE WINDOW
• The DCOK comparator might not be triggered even though
the output voltage exceeds ± 5% limits at load transients.
This is because the feedback network of the error amplifier
filters out part of the transients and the EAI only sees the
remaining portion that is still within the limits, as illustrated in
Figure 12. The lower the “zero (1/RC)” of the error amplifier,
the larger the portion of the transient that is filtered out.
Thermal Pad (in QFN only)
• In the QFN package, the pad underneath the center of
the IC is a “floating” thermal substrate. The PCB “thermal
land” design for this exposed die pad should include
thermal vias that drop down and connect to one or more
buried copper plane(s). This combination of vias for
vertical heat escape and buried planes for heat
spreading allows the QFN to achieve its full thermal
potential. This pad should be connected to a low noise
copper plane such as Vss.
• Refer to TB389 for design guidelines.
14
FN6762.0
September 2, 2008