ISL6551IREC Datasheet, PDF (10/23 Pages) Intersil Corporation – ZVS Full Bridge PWM Controller

ISL6551IREC
• VDDP1 and VDDP2 are the bias supplies for the upper
drivers and the lower drivers, respectively. They should be
decoupled with ceramic capacitors to the PGND pin.
• Heavy copper should be attached to these pins for a better
heat spreading.
IC GNDs (VSS, PGND)
• VSS is the reference ground, the return of VDD, of all control
circuits and must be kept away from nodes with switching
noises. It should be connected to the PGND in only one
location as close to the IC as practical. For a secondary side
control system, it should be connected to the net after the
output capacitors, i.e., the output return pinout(s). For a
primary side control system, it should be connected to the net
before the input capacitors, i.e., the input return pinout(s).
• PGND is the power return, the high-current return path of both
VDDP1 and VDDP2. It should be connected to the SOURCE
pins of two lower power switches or the RETURNs of external
drivers as close as possible with heavy copper traces.
• Copper planes should be attached to both pins.
Undervoltage Lockout (UVLO)
• UVLO establishes an orderly start-up and verifies that VDD is
above the turn-on threshold voltage (VDD_ON). All the drivers
are held low during the lockout. UVLO incorporates
hysteresis VDD_HYS to prevent multiple startup/shutdowns
while powering up.
• UVLO limits are not applicable to VDDP1 and VDDP2.
Bandgap Reference (BGREF)
• The reference voltage VREF is generated by a precision
bandgap circuit.
• This pin must be pulled up to VDD with a resistance of
approximately 399kΩ for proper operation. For additional
reference loads (no more than 1mA), this pull-up resistor
should be scaled accordingly.
• This pin must also be decoupled with an 0.1µF low ESR
ceramic capacitor.
Clock Generator (CT, RD)
• This free-running oscillator is set by two external
components, as shown in Figure 2. A capacitor at CT is
charged and discharged with two equal constant current
sources and fed into a window comparator to set the clock
frequency. A resistor at RD sets the clock dead time. RD and
CT should be tied to the VSS pin on their other ends as close
as possible. The corresponding CT for a particular frequency
can be selected from Figure 1.
• The switching frequency (Fsw) of the power train is half of the
clock frequency (Fclock), as shown in Equation 1.
Fsw
=
F_-----c_---l_--o_----c_---k_--
2
(EQ. 1)
3,000
+0°C
2,500 _+60°C
+120°C
2,000
1,500
1,000
500
0
10
100
1,000
CT (pF)
RECOMMENDED RANGE
FIGURE 1. CT vs FREQUENCY
10,000
RD
SET CLOCK
DEAD TIME (DT)
RD
VDD-
I_CT
VMAX
- ^OUT
+
CLK
CT
S
Q
Q
CT
VMIN
- ^OUT
+
RQ
Q
I_CT
CLK
DT
DT
FIGURE 2. SIMPLIFIED CLOCK GENERATOR CIRCUIT
10
FN6762.0
September 2, 2008