ISL6551IREC Datasheet, PDF (13/23 Pages) Intersil Corporation – ZVS Full Bridge PWM Controller

ISL6551IREC
eliminates response degrading delays which would be
caused if filtering of the current feedback was incorporated.
The current ramp is blanked out during the resonant delay
period because no switching occurs in the lower FETs. The
leading edge blanking function will not be activated until the
soft-start (CSS) reaches over 400mV, as illustrated in Figures
5 and 9. The leading edge blanking (LEB) function can be
disabled by tying the R_LEB pin to VDD, i.e., LEB = 1. Never
leave the pin floating.
• The blanking time can be estimated with Equation 9, whose
relationship can be seen in Figure 8. The percentages in the
figure are the tolerances at the two endpoints of the curve.
t_LEB = 2 x R_LEB / kΩ + 15 (ns)
(EQ. 9)
300
250
200
150
100 +51%
50 ^-11%
0
20
40
60
80
100
R_LEB (kΩ)
FIGURE 8. R_LEB vs t_LEB
+20%
-18%
120
140
Ramp Adjust (R_RA, ISENSE)
• The ramp adjust block adds an offset component (200mV)
and a slope adjust component to the ISENSE signal
before processing it at the PWM Logic block, as shown in
Figure 9. This ensures that the ramp voltage is always
higher than the OAGS (ground sensing op amp) minimum
voltage to achieve a “zero” state.
• It is critical that the input signal to ISENSE decays to zero
prior to or during the clock dead time. The level-shifting
and capacitive summing circuits in the RAMP ADJUST
block are reset during the dead time. Any input signal
transitions that occur after the rising edge of CLK and prior
to the rising edge of RESDLY can cause severe errors in
the signal reaching the PWM comparator.
• Typical ramp values are hundreds of mV over the period
on a 3V full scale current. Too much ramp makes the
controller look like a voltage mode PWM, and too little
ramp leads to noise issues (jitter). The amount of ramp
(Vramp), as shown in Figure 9, is programmed with the
R_RA resistor and can be calculated with Equation 10.
V_ramp = BGREF x dt /(R_RA x 500E-12) (V)
(EQ. 10)
where dt = Duty Cycle/Fsw - t_LEB (s). Duty cycle is
discussed in detail in application note AN1002.
• The voltage representation of the current flowing through
the power train at ISENSE pin is normally scaled such that
the desired peak current is less than or equal to
Vclamp-200mV-Vramp, where the clamping voltage is set
at the CSS pin.
VDD
0.1µ
399k
R_RA
BGREF
R_RA
ISENSE
ADD RAMP
ADJ_RAMP
+
-
200mV
R_LEB
R_LEB
SET
BLANKING
TIME
RESDLY
LEB
SSL
(SEE FIG. 4)
ADJ_RAMP
RAMP_OUT
(TO PWM
200mV
0
ISENSE
COMPARATOR)
RAMP_OUT
200mV
BLANK
RESDLY
0
X
1
1
LEB
X
0
1
X
SSL RAMP_OUT
X
BLANK
0
BLANK
X
NO BLANK
1
NO BLANK
FIGURE 9. SIMPLIFIED RAMP ADJUST AND LEADING EDGE BLANKING CIRCUITS
13
FN6762.0
September 2, 2008