ISL6551IREC Datasheet, PDF (3/23 Pages) Intersil Corporation – ZVS Full Bridge PWM Controller

ISL6551IREC
Functional Pin Description
PIN #
26
27
28
1
PIN SYMBOL
VSS
CT
RD
R_RESDLY
FUNCTION
Reference ground. All control circuits are referenced to this pin.
Set the oscillator frequency, up to 1MHz.
Adjust the clock dead time from 50ns to 1000ns.
Program the resonant delay from 50ns to 500ns.
2
R_RA
Adjust the ramp for slope compensation (from 50mV to 250mV).
3
ISENSE
The pin receives the current information via a current sense transformer or a power resistor.
4
PKILIM
Set the overcurrent limit with the bandgap reference as the trip threshold.
5
BGREF
Precision bandgap reference, 1.263V ±2% overall recommended operating conditions.
6
R_LEB
Program the leading edge blanking from 50ns to 300ns.
7
CS_COMP
Set a low current sharing loop bandwidth with a capacitor.
8
CSS
Program the rise time and the clamping voltage with a capacitor and a resistor, respectively.
9
EANI
Non-inverting input of Error Amp. It is clamped by the voltage at the CSS pin (Vclamp).
10
EAI
Inverting input of Error Amp. It receives the feedback voltage.
11
EAO
Output of Error Amp. It is clamped by the voltage at the CSS pin (Vclamp).
12
SHARE
This pin is the SHARE BUS connecting with other unit(s) for current share operation.
13
14
15
16, 17
18, 19
20, 21
22
23, 24
25
LATSD
DCOK
ON/OFF
SYNC2, SYNC1
LOWER2, LOWER1
UPPER2, UPPER1
PGND
VDDP2, VDDP1
VDD
The IC is latched off with a voltage greater than 3V at this pin and is reset by recycling VDD.
Power-Good indication with a ±5% window.
This is an Enable pin that controls the states of all drive signals and the soft-start.
These are the gate control signals for the output synchronous rectifiers.
Both lower drivers are PWM-controlled on the trailing edge.
Both upper drivers are driven at a fixed 50% duty cycle.
Power Ground. High current return paths for both the upper and the lower drivers.
Power is delivered to both the upper and the lower drivers through these pins.
Power is delivered to all control circuits including SYNC1 and SYNC2 via this pin.
3
FN6762.0
September 2, 2008