ISL6551IREC Datasheet, PDF (7/23 Pages) Intersil Corporation – ZVS Full Bridge PWM Controller

ISL6551IREC
Electrical Specifications
These specifications apply for VDD = VDDP = 12V and T_A = 0°C to +85°C, Unless Otherwise Stated.
Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature
limits established by characterization and are not production tested. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
CURRENT SHARE (SHARE, CS_COMP) (Note 3)
Voltage Offset Between Error Amp Voltage of
Master and Slave
Vcs_offset SHARE = 30k
30
mV
Maximum Source Current to External Reference Ics_source SHARE = 30k
190
μA
Maximum Correctable Deviation In Reference
Voltage Between Master and Slave
SHARE = 30K, Rsource = 1k,
OUTPUT REFERENCE = 1 to 5V,
(See Figure 10)
190
mV
Share/Adjust Loop Bandwidth
CS BW CS_COMP = 0.1µF
500
Hz
DC OK (DCOK)
Sink Current
Saturation Voltage
Input Reference
I_DCOK
V_SATDCOK I_DCOK = 5mA
Vref_in
5 mA
0.4 V
1
5
V
Threshold (Relative to Vref_in)
OV (Figure 11)
5
%
Recovery (Relative to Vref_in)
OV (Figure 11)
3
%
Threshold (Relative to Vref_in)
UV (Figure 11)
-5
%
Recovery (Relative to Vref_in)
UV (Figure 11)
-3
%
Transient Rejection (Note 3)
TRej 100mV transient on Vout (system implicit rejection
250
μs
and feedback network dependence (Figure 12)
NOTE:
3. Limits established by characterization and are not production tested.
7
FN6762.0
September 2, 2008