ISL6551IREC Datasheet, PDF (11/23 Pages) Intersil Corporation – ZVS Full Bridge PWM Controller

ISL6551IREC
• Note that the capacitance of a scope probe (~12pF for
single-ended) would induce a smaller frequency at the CT
pin. It can be easily seen at a higher frequency. An
accurate operating frequency can be measured at the
outputs of the bridge/synchronous drivers.
The dead time is the delay to turn on the upper FET
(UPPER1/UPPER2) after its corresponding lower FET
(LOWER1/LOWER2) is turned off when the bridge is
operating at maximum duty cycle in normal conditions, or is
responding to load transients or input line dipping conditions.
This helps to prevent shoot through between the upper FET
and the lower FET that are located at the same side of the
bridge. The dead time can be estimated using Equation 2:
DT = ^{M-------k×}---_Ω--R-----D-- (ns)
(EQ. 2)
where M = 11.4 (VDD = 12V), 11.1(VDD = 14V), and 12
(VDD = 10V), and RD is in kΩ. This relationship is shown in
Figure 3.
2.0
1.6
1.2
0.8
0.4
0
0 ^{20 40 60 80 100 120 140 160}
RD (kΩ)
FIGURE 3. RD vs DEAD TIME (VDD = 12V)
Error Amplifier (EAI, EANI, EAO)
• This amplifier compares the feedback signal received at
the EAI pin to a reference signal set at the EANI pin and
provides an error signal (EAO) to the PWM Logic. The
feedback loop compensation can be programmed via
these pins.
• Both EANI and EAO are clamped by the voltage (Vclamp)
set at the CSS pin, as shown in Figure 5. Note that the
diodes in the functional block diagram represent the clamp
function of the CSS in a simplified way.
Soft-Start (CSS)
• The voltage on an external capacitor charged by an internal
current source I_SS is fed into a control pin on the error
amplifier. This causes the Error Amplifier to: 1) limit the
EAO to the soft-start voltage level; and 2) over-ride the
reference signal at the EANI with the soft-start voltage,
when the EANI voltage is higher than the soft-start voltage.
Thus, both the output voltage and current of the power
supply can be controlled by the soft-start.
• The clamping voltage determines the cycle-by-cycle peak
current limiting of the power supply. It should be set above
the EANI and EAO voltages and can be programmed by
an external resistor, as shown in Figure 5 using
Equation 3.
Vclamp = Rcss • Iss (V)
(EQ. 3)
• Per Equation 3, the clamping voltage is a function of the
charge current Iss. For a more predictable clamping
voltage, the CSS pin can be connected to a reference
based clamp circuit, as shown in Figure 4. To make the
Vclamp less dependent on the soft-start current (Iss), the
currents flowing through R1 and R2 should be scaled
much greater than Iss. The relationship of this circuit can
be found in Equation 4.
V_REF
R1
CSS
R2
FIGURE 4. REFERENCE-BASED CLAMP CIRCUIT
Vc
l
am
p
≈
Is
s
•
-R----1-----^×-----R-----2--
R1 + R2
+
Vref
•
--------R-----2---------
R1 + R2
(EQ. 4)
• The soft-start rise time (t_ss) can be calculated with
Equation 5. The rise time (t_rise) of the output voltage is
approximated with Equation 6.
t_rise
=
-E----A----N-----I---^×-----C-----s----s-
Iss
(s)
(EQ. 6)
t_ss
=
V-----c---l--a----m------p----×_{-----C-----s---s--}
Iss
(s)
(EQ. 5)
Drivers (Upper1, Upper2, Lower1, Lower2)
• The two upper drivers are driven at a fixed 50% duty cycle
and the two lower drivers are PWM-controlled on the
trailing edge while the leading edge employs resonant delay.
They are biased by VDDP1 and VDDP2, respectively.
• Each driver is capable of driving capacitive loads up to CL at
1MHz clock frequency and higher loads at lower frequencies
on a layout with high effective thermal conductivity.
• The UVLO holds all the drivers low until the VDD has
reached the turn-on threshold VDD_ON.
• The upper drivers require assistance of external level-shifting
circuits, such as Intersil’s HIP2100 or pulse transformers to
drive the upper power switches of a bridge converter.
11
FN6762.0
September 2, 2008