ISL6551IREC Datasheet, PDF (15/23 Pages) Intersil Corporation – ZVS Full Bridge PWM Controller

ISL6551IREC
18k
15N
EAI R
C
VOUT
-
1k _{EANI +}
EAO
1.10V
1.00V
VOUT
0.90V
1.05V
EAI
1.00V
0.95V
FIGURE 12. OUTPUT TRANSIENT REJECTION
Additional Applications Information
Table 11 highlights parameter setting for the ISL6551IREC.
Designers can use this table as a design checklist. For
detailed operation of the ISL6551IREC, see “Block/Pin
Functional Descriptions” on page 9.
Figure 13 shows the block diagram of a power supply system
employing the ISL6551IREC full bridge controller. The
ISL6551IREC not only is a full bridge PWM controller but also
can be used as a push-pull PWM controller. Users can design
a power supply by selecting appropriate blocks in the System
Blocks Chart based on the power system requirements.
Figures 13A, 14A, 15A, 16A, 17A, 18A, 19, 20A, 21, 22A, and
24A have been used in the 200W telecom power supply
reference design, which can be found in the Application Note
AN1002. To meet the specifications of the power supply,
minor modifications of each block are required. To take full
advantage of the integrated features of the ISL6551IREC,
“secondary side control” is recommended.
TABLE 1. PARAMETER SETTING HIGHLIGHTS/CHECKLIST
PARAMETER
PIN NAME
FORMULA OR SETTING HIGHLIGHT
UNIT
Frequency
CT
Set 50% Duty Cycle Pulses with a fixed frequency
kHz
Dead Time
RD
DT = MxRD/kΩ, where M = 11.4
ns
Resonant Delay
R_RESDLY
t_RESDLY = 4.01xR_RESDLY/kΩ + 13
ns
Ramp Adjust
R_RA
Vramp = BGREF/(R_RAx500E-12)xdt
V
Current Sense
ISENSE
<Vclamp - 200mV - Vramp
V
Peak Current
PKILIM
<BGREF and slightly higher than Vclamp
V
Bandgap Reference
BGREF
1.263V ±2%, 399kΩ pull-up, No more than 100µA load
V
Leading Edge Blanking
R_LEB
t_LEB = 2 x R_LEB/kΩ + 15, never leave it floating
ns
Current Share Compensation
CS_COMP
0.1µ for a low current loop bandwidth (100 - 500Hz)
Hz
Soft-Start & Output Rise Time
Clamp Voltage (Vclamp)
CSS
CSS
t_ss = VclampxCss/Iss, t_rise = EANI x CSS/Iss, Iss = 10µA ±20%
S
Vclamp = IssxRcss, or Reference-based clamp
V
Error Amplifier
EANI, EAI, EAO EANI, EAO < Vclamp
V
Share Support
SHARE
30K load and a resistor (1k, typ.) between EANI and OUTPUT REF. -
Latching Shutdown
LATSD
Latch IC off at > 3V
V
Power-Good
DCOK
±5% with hysteresis, Sink up to 5mA, transient rejection
V
IC Enable
ON/OFF
Turn on/off at TTL level
V
Reference Ground
VSS
Connect to PGND in only one single point
-
Power Ground
PGND
Single point to VSS plane
-
Upper Drivers
UPPER1, UPPER2 Capacitive load up to 1.6nF at Fsw = 500kHz
-
Lower Drivers
LOWER1, LOWER2 Capacitive load up to 1.6nF at Fsw = 500kHz
-
Synchronous Drive Signals
SYNC1, SYNC2 Capacitive load up to 20pF at Fsw = 500kHz
-
Bias for Control Circuits
VDD
12V ±10%, 0.1µF decoupling capacitor
V
Biases for Bridge Drivers
VDDP1, VDDP2 Need decoupling capacitors
V
NOTE: VDD = 12V at room temperature, unless otherwise stated.
FIGURE #
1, 2
3
7
-
-
6
-
8, 9
10
4
4, 5
-
-
-
11, 12
-
-
-
-
-
-
-
-
15
FN6762.0
September 2, 2008