HMP8117_07 Datasheet, PDF (9/45 Pages) Intersil Corporation – NTSC/PAL Video Decoder

HMP8117
for gamma = 2.2:
for R′B′ < 0.0812*31, G′ < 0.0812*63
R = (31)((R′/31)/4.5)
G = (63)((G′/63)/4.5)
B = (31)((B′/31)/4.5)
for R′B′ >= 0.0812*31, G′ >= 0.0812*63
R = (31)(((R′/31) + 0.099)/1.099)^2.2
G = (63)(((G′/63) + 0.099)/1.099)^2.2
B = (31)(((B′/31) + 0.099)/1.099)^2.2
for gamma = 2.8:
R = (31)(R′/31)^2.8
G = (63)(G′/63)^2.8
B = (31)(B′/31)^2.8
Built-in Video Generation
The decoder can be configured to output a full-screen of built-in
blue, black or 75% color bar patterns. The type of pattern
generated is determined by bits 2-1 of the OUTPUT FORMAT
register 02_H. When built-in video generation is not desired, the
bits need to be set for normal operation to pass decoded video.
If the decoder is currently locked to a video source on the
input, the output data timing will be based on the input video
source. If an input video source is not detected, internally-
generated output data timing will be used. The following
table lists the data codes output for each built-in video
pattern in YCbCr format.
TABLE 2. BUILT-IN VIDEO PATTERN DATA CODES
PATTERN: COLOR
Y
Cb
Cr
75% Color Bar: White B4_H
80_H
80_H
Yellow A2_H
2C_H
8E_H
Cyan 83_H
9C_H
2C_H
Green 70_H
48_H
3A_H
Magenta 54_H
B8_H
C6_H
Red 41_H
64_H
D4_H
Blue 23_H
D4_H
72_H
Black 10_H
80_H
80_H
Blue Screen: Blue 4B_H
D9_H
88_H
Black Screen: Black 10_H
80_H
80_H
Pixel Port Timing
The the timing and format of the output data and control
signals is presented in the following sections. Refer to the
section “CYCLE SLIPPING AND REAL-TIME PIXEL
JITTER” for PLL and interface considerations.
HSYNC and VSYNC Timing
The HSYNC and VSYNC output timing is VMI v1.4 compatible.
Figures 3-6 illustrate the video timing. The leading edge of
HSYNC is synchronous to the video input signal and has a
fixed latency due to internal pipeline processing. The pulse
width of the HSYNC is defined by the END HSYNC register
36_H, where the trailing edge of HSYNC has a programmable
delay of 0-510 CLK2 cycles from the leading edge.
The leading edge of VSYNC is asserted approximately half way
through the first serration pulse of each field. An accumulator is
used to detect a low-time period within the serration pulse.
Since the leading edge of VSYNC is detected, it should not be
used for timing with respect to HSYNC or BLANK.
The trailing edge of VSYNC implements the VMI handshake
with HSYNC in order to determine field information without
using the FIELD pin. For an odd field, the trailing edge of
VSYNC is 5 ±1 CLK2 cycles after the trailing edge of the
HSYNC that follows the last equalization pulse. Refer to
Figures 3 and 5. For an even field, the trailing edge of VSYNC
is 5 ±1 CLK2 cycles after the leading edge of the HSYNC that
follows the last equalization pulse. Refer to Figures 4 and 6.
Field Timing
When field information can be determined from the input
video source, the FIELD output pin reflects the video source
field state. When field information cannot be determined
from the input video source, the FIELD output pin alternates
its state at the beginning of each field. FIELD changes state
5±1 CLK2 cycles before the leading edge of VSYNC.
NTSC(M) LINE# 524
525
1
2
3
4
5
6
7
8
9
10
PAL(M) LINE# 521
522
523
524
525
1
2
3
4
5
6
7
VIDEO
INPUT
HSYNC
VSYNC
FIELD
‘EVEN’ FIELD
‘ODD’ FIELD
FIGURE 3. NTSC(M) AND PAL(M) ODD FIELD TIMING
9
FN4643.3
April 19, 2007