HMP8117_07 Datasheet, PDF (44/45 Pages) Intersil Corporation – NTSC/PAL Video Decoder

HMP8117
Electrical Specifications V_CC = V_AA = 5.0V, T_A = +25°C (Continued)
PARAMETER
SYMBOL
TEST CONDITION
MIN
TYP
MAX UNITS
GENLOCK PERFORMANCE
Horizontal Locking Time
t_LOCK
Time from Initial Lock
Acquisition to an Error of
1 Pixel. (Note 42)
2
3
Fields
Long-Term horizontal Sync
Lock Range
Range over specified pixel jitter is
±-
maintained. Assumes line time changes
by amount indicated slowly between
over one field. (Note 42)
5
%
Number of Missing Horizontal Syncs
Before Lost Lock Declared
H_{SYNC LOST}
Programmable via register 04_H
(Note 42)
1 or 12 1 or 12 1 or 12 HSYNCs
Number of Missing Vertical Syncs
Before Lost Lock Declared
V_{SYNC LOST}
1 or 3
1 or 3
1 or 3 VSYNCs
Long-Term Color Subcarrier
Lock Range
Range over color subcarrier locking
time and accuracy specifications are
maintained. Subcarrier frequency
changes by amount indicated slowly
over 24 hours. (Note 42)
±200
±400
Hz
Vertical Sample Alignment
(Notes 42, 44)
1/8
Pixel
10
ns
NOTES:
42. Guaranteed by design or characterization.
43. Test performed with C_L = 40pF, I_OL = 4mA, I_OH = -4mA. Input reference level is 1.5V for all inputs. V_IH = 3.0V, V_IL = 0V.
44. Since the HMP8117 does not generate the sample clock, any clock jitter present on the CLK2 input will directly translate to pixel jitter on the
output data. The Vertical Sample Alignment parameter specifies the spatial pixel alignment from one scan line to the next using a stable CLK2
source.
44
FN4643.3
April 19, 2007