HMP8117_07 Datasheet, PDF (40/45 Pages) Intersil Corporation – NTSC/PAL Video Decoder

HMP8117
Applications Information
Direct Interface to Video Encoders
Direct interface to a video encoder will induce pixel jitter in
the output video and is therefore not recommended as a
primary data interface. The jitter will occur with all decoder
output formats, including BT.656. However, pixel jitter may
be acceptable for some applications; such as a “preview
mode” prior to image capture or compression. For more
detail, reference“Cycle Slipping and Real-Time Pixel Jitter”
on page 7.
Decoder Upgrades
The following table describe the impacts to pins for
upgrading from the HMP8112/A or HMP8115 to the
HMP8117.
TABLE 67. UPGRADING FROM HMP8112/A OR HMP8115
Pin # HMP8112/15 Pin
HMP8117 Impact
28
GAIN_CNTL
(Now RSET)
Use single 12.1k resistor to AGND.
Remove any decoupling caps.
78
DEC_T
Change to single 1.0uF capacitor
(Now REF_CAP) (1206-size XR7-type) to AGND.
29
CCLAMP_CAP Change to 0.1uF capacitor.
(Now CCAP)
76
LCLAMP_CAP Change to 0.1uF capacitor.
(Now LCAP)
9,8,19 L_OUT,
L_ADIN, and C
Recommend use of new anti-alias
filter from Reference Schematic.
27
WPE
(Now SA)
Pull low for I2C address compatibility
with HMP8112/A.
44
DVCC/NC
Pin actually NC on HMP8112/A.
(Now INTREQ) Float or use 10K pullup to VCC.
61
DGND/NC
Pin actually NC on HMP8112/A.
(Now VBIVALID) Float or use 10K pullup to VCC.
13
CLK2
(Now NC)
Trace may be deleted to reduce
reflections on CLK2 at pin 38.
30, 32, DEC_L, DGND, Pins no longer used (NC). Capacitors
73, 77 DGND, AGC_CAP used at these pins may be removed.
Typical Programming Sequence
The following pseudo code provides a typical programming
sequence to initialize the HMP8117 using the default 16-bit
YCbCr output data format.
SetReg 0x1F = 0x80 // Soft Reset
SetReg 0x37 = 0x90 // Wider HSYNC Detect Window
SetReg 0x42 = 0x30 // Recommended Value
SetReg 0x50 = 0x21 // Slower PFG
SetReg 0x52 = 0x22 // Recommended Value
SetReg 0x53 = 0xF0 // Large AGC Hysteresis
SetReg 0x03 = 0xC0 // Enable Data/Timing Outputs
PCB Layout Considerations
A PCB board with a minimum of 4 layers is recommended,
with layers 1 and 4 (top and bottom) for signals and layers
2 and 3 for power and ground. The PCB layout should
implement the lowest possible noise on the power and
ground planes by providing excellent decoupling. The
optimum layout places the HMP8117 as close as possible
to the power supply connector and the video input
connector. Place external components as close as possible
to the appropriate pin using short, wide traces.
ANALOG POWER PLANE
The analog power plane (V_AA) is recommended to be
separate from the common board digital power plane (V_CC)
with a gap between the two planes of at least 1/8 inch. The
V_AA plane should be connected to the V_CC plane at a single
point though a low-resistance ferrite bead, such as a
Ferroxcube 5659065-3B, Fair-Rite 2743001111, or TDK
BF45-4001. The ferrite bead provides resistance to
switching currents, improving the performance of HMP8117.
If a separate linear regulator is used to provide power to the
analog power plane, the power-up sequence should be
designed to ensure latch up will not occur. A separate linear
regulator is recommended if the power supply noise on the V_AA
pins exceeds 200mV.
ANALOG GROUND PLANE
A separate analog ground (AGND) plane is recommended
with a single point connection to the digital ground (GND)
plane using a ferrite bead as mentioned above.
POWER SUPPLY DECOUPLING
Decouple each V_AA and V_CC pin to the appropriate ground
plane using a 0.1μF ceramic chip capacitor. Bulk decouple
the power planes using a 1.0μF ceramic chip capacitor
located at each corner of the device. (One capacitor placed
at the top left corner for V_AA and three capacitors placed at
the other corners for V_CC.) A single 47μF decoupling
capacitor for the analog power plane may also be used to
control excessive low-frequency power supply ripple. See
Figure 20, HMP8117 Reference Schematics.
ANALOG SIGNALS
Traces containing digital signals should not be routed over,
under, or adjacent to the analog output traces to minimize
cross-talk. If this is not possible, coupling can be minimized
by routing the digital signals at a 90 degree angle to the
analog signals. The analog traces should also not overlay
the V_CC power plane to maximize high-frequency power
supply rejection.
Evaluation Board
HMPVIDEVAL/ISA
The HMPVIDEVAL/ISA board provides a complete video
frame-grabber platform to evaluate all modes of the video
decoder and encoder. The ISA style PC add-in board
supports a complete Windows 95 software application to
easily operate all features of the evaluation platform.
40
FN4643.3
April 19, 2007