HMP8117_07 Datasheet, PDF (36/45 Pages) Intersil Corporation – NTSC/PAL Video Decoder

HMP8117
TABLE 57. END V_BLANK REGISTER
BIT
NO.
FUNCTION
SUB ADDRESS = 35_H
DESCRIPTION
RESET
STATE
7-0
Negate BLANK
Output Signal
This 8-bit register specifies the line number to negate BLANK each field.
12_H
For NTSC operation, it occurs on line (n + 5) on odd fields and line (n + 268) on even fields. For
PAL operation, it occurs on line (n + 5) on odd fields and line (n + 318) on even fields.
TABLE 58. END HSYNC REGISTER
BIT
NO.
FUNCTION
SUB ADDRESS = 36_H
DESCRIPTION
RESET
STATE
7-0
Negate HSYNC
This 8-bit register specifies the horizontal count at which to negate HSYNC each scan line.
30_H
Output Signal
Values may range from 0 (0000 0000) to 510 (1111 1111) CLK2 cycles. The leading edge of
HSYNC is count 00_H.
TABLE 59. HSYNC DETECT WINDOW REGISTER
BIT
NO.
FUNCTION
SUB ADDRESS = 37_H
DESCRIPTION
RESET
STATE
7-0
Horizontal Sync
This 8-bit register specifies the width of the timing window (in 1x clock samples) for the digital
20_H
Detect Window
PLL to accept horizontal sync pulses in each line. The window is centered about where the
horizontal sync pulse should be located.
(Use 90_H)
If the horizontal sync pulse falls inside the window, the digital PLL maintains normal lock timing.
If the horizontal sync pulse falls outside this window, the digital PLL will to enter the horizontal
lock acquisition mode based on the current setting for bits 3-2 of register 04_H. Recommend
changing this register to 90_H following reset in order to widen the window for poorly timed input
video sources.
TABLE 60. MV CONTROL
BIT
NO.
FUNCTION
SUB ADDRESS = 41_H
DESCRIPTION
RESET
STATE
7
MV Stripe Detection Set to “1” to enable the detection and bypass of the MV Color Striping component. If this bit is
0_B
and Bypass Enable not enabled and the MV Color Striping component exists on the input signal, artifacts will be
clearly visible as horizontal streaks in the output data. This bit must be enabled for the MV
Detection Status of register 0E_H to be updated.
6
MV PSP Detection Set to “1” to enable detection of the MV Pseudo Sync Pulse (PSP)
0_B
Enable
component. If the MV PSP component exists on the input signal, this bit must be enabled for the
MV Detection Status of register 0E_H to be updated.
5-3
MV PSP Detection Defines the number of extra sync pulses required before declaring the Pseudo Sync Pulse (PSP)
100_B
Count
component in the MV Detection Status of register 0E_H. The PSP component must also be
present for the number of fields defined in bits 2-0 below.
2-0
MV Detection
Field Count
Defines the minimum number of fields that an MV component must be present for in order to
change the MV Detection Status of register 0E_H. Add 2 to bits 2-0 to obtain the minimum field
count. Ex: The default of 110_B is actually 6 + 2 = 8 fields.
110_B
TABLE 61. RESERVED
BIT
NO.
FUNCTION
SUB ADDRESS = 42_H
DESCRIPTION
RESET
STATE
7-0
Reserved
Set bits 5-4 to 11_B for optimum performance.
00_H
(Use 30_H)
36
FN4643.3
April 19, 2007