HMP8117_07 Datasheet, PDF (7/45 Pages) Intersil Corporation – NTSC/PAL Video Decoder

HMP8117
operation. Use of a PLL to generate a “Line Locked” CLK2
input based on the input video is not recommend. (See the
following section.)
Cycle Slipping and Real-Time Pixel Jitter
The decoder’s digital PLL allows it to maintain lock and
provide high quality Y/C separation even on the poorest
quality input video signals. However, this architecture does
not provide a “Line Lock Clock” output and should not be
used as a timing master for direct interface to another video
encoder in a system.
Since the decoder uses a fixed CLK2 input frequency, the
output pixel rate must be periodically adjusted to
compensate for any frequency error between CLK2 and the
input video signal. This output pixel rate adjustment is
referred to as cycle slipping. Since the decoder has an
output data FIFO, all cycle slipping can be deferred until the
next horizontal blanking interval. This guarantees a
consistent number of pixels during the active video region.
Due to cycle slipping, the output timing and data will exhibit a
nominal real-time (line-to-line) pixel jitter of one CLK2 period.
Although the sample rate converter maintains a 1/8 pixel
vertical sample alignment, the output data must be routed to
a frame buffer or video compression chip in order remove
the effects of cycle slipping. (The frame buffer or
compression chip serves as a time base corrector.)
By directly interfacing the decoder to a video encoder, the
output video signal will directly reflect the real-time pixel jitter
effects of the decoder output timing. The jitter effects can be
visualized on a CRT monitor using a static image containing
patterns with sharp vertical edges. The edges will appear
more “ragged” when compared to the input video signal. The
severity of this visual effect relates directly to the frequency
error between CLK2 and the input video signal. It is nearly
impossible to completely match CLK2 with the input video
signal. Therefore, a direct decoder to encoder interface is
not recommended.
The use of an external PLL to generate a “Line Locked”
CLK2 input derived from the input video signal is also not
recommended, since this will defeat the internal digital PLL
and result in pixel decoding errors.
Digital Processing of Video
Once the luma and chroma have been separated the
HMP8117 then performs programmable modifications (i.e.
contrast, coring, color space conversions, color AGC, etc.) to
the decoded video signal.
UV to CbCr Conversion
The baseband U and V signals are scaled and offset to
generate a nominal range of 16-240 for both the Cb and Cr
data.
Digital Color Gain Control
There are four types of color gain control modes available:
no gain control, automatic gain control, fixed gain control,
and freeze automatic gain control.
If “no gain control” is selected, the amplitude of the color
difference signals (CbCr) is not modified, regardless of
variations in the color burst amplitude. Thus, a gain of 1x is
always used for Cb and Cr.
If “automatic gain control” is selected, the amplitude of the
color difference signals (CbCr) is compensated for variations
in the color burst amplitude. The burst amplitude is averaged
with the two previous lines having a color burst to limit line-
to-line variations. A gain of 0.5x to 4x is used for Cb and Cr.
If “fixed gain control” is selected, the amplitude of the color
difference signals (CbCr) is multiplied by a constant,
regardless of variations in the color burst amplitude. The
constant gain value is specified by the COLOR GAIN
register 1C_H. A gain of 0.5x to 4x is used for Cb and Cr.
Limiting the gain to 4x limits the amount of amplified noise.
If “freeze automatic gain control” is selected, the amplitude of
the color difference signals (CbCr) is multiplied by a constant.
This constant is the value the AGC circuitry generated when the
“freeze automatic gain” command was selected.
Color Killer
If “enable color killer” is selected, the color output is turned
off when the running average of the color burst amplitude is
below approximately 25% of nominal for four consecutive
fields. When the running average of the color burst
amplitude is above approximately 25% of nominal for four
consecutive fields, the color output is turned on. The color
output is also turned off when excessive phase error of the
chroma PLL is present.
If “force color off” is selected, color information is never
present on the outputs.
If “force color on” is selected, color information is present on
the outputs regardless of the color burst amplitude or
chroma PLL phase error.
Y Processing
The black level is subtracted from the luminance data to
remove sync and any blanking pedestal information.
Negative values of Y are supported at this point to allow
proper decoding of “below black” luminance levels.
Scaling is done to position black at 8-bit code 0 and white at
8-bit code 219.
A chroma trap filter may be used to remove any residual color
subcarrier from the luminance data. The center frequency of
the chroma trap is automatically determined from the video
standard being decoded. The chroma trap should be disabled
during S-video operation to maintain maximum luminance
bandwidth. Alternately, a 3MHz low-pass filter may be used to
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FN4643.3
April 19, 2007