HMP8117_07 Datasheet, PDF(14/45 Page) Intersil Corporation

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HMP8117_07 Datasheet, PDF (14/45 Pages) Intersil Corporation – NTSC/PAL Video Decoder

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CLK

DVALID

HMP8117

P15-P8

P7-P0

Cb0

Cr0

Cb2

Cr2

Cb4

NOTES:

tDVLD

12. Y0 is the first active luminance pixel of a line. Cb0 and Cr0 are first active chrominance pixels in a line. Cb and Cr will alternate every cycle due

to the 4:2:2 subsampling.

13. BLANK is asserted per Figure 7.

14. DVALID is asserted for every valid pixel during both active and blanking regions.

FIGURE 12. OUTPUT TIMING FOR 16-BIT YCbCr MODE (DVLD_LTC = 0, DVLD_DCYC = 1)

CLK

DVALID

BLANK

P15-P11

[P14-P10]

P10-P5

[P9-P5]

P4-P0

NOTES:

tDVLD

15. BLANK is asserted per Figure 7.

16. DAVLID is asserted for every valid pixel during both active and blanking regions. DVALID is not a 50% duty cycle synchronous output and will

appear to jitter as the Output Sample Rate converter adjusts the output timing for various data rates and clock frequency inputs.

FIGURE 13. OUTPUT TIMING FOR 16-BIT [15-BIT] RGB MODE (DVLD_LTC = 0, DVLD_DCYC = 1)

8-Bit BT.656 Output

For the BT.656 output mode, data is output following each

rising edge of CLK2. The BT.656 EAV and SAV formats are

shown in Table 5 and the pixel output timing is shown in

Figure 14. The EAV and SAV timing is determined by the

programmed horizontal and vertical blank timing.

BLANK, HSYNC, VSYNC, DVALID, VBIVALID, and FIELD

are output following the rising edge of CLK2.

During the blanking intervals, the YCbCr outputs have a

value of 16 for Y and 128 for Cb and Cr, unless ancillary data

is present.

FN4643.3

April 19, 2007

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